Full Text:   <2069>

Summary:  <1547>

CLC number: TN432

On-line Access: 2016-08-31

Received: 2015-09-08

Revision Accepted: 2016-02-17

Crosschecked: 2016-08-15

Cited: 0

Clicked: 4418

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Ji-zhong SHEN

http://orcid.org/0000-0002-9031-2379

-   Go to

Article info.
Open peer comments

Frontiers of Information Technology & Electronic Engineering  2016 Vol.17 No.9 P.962-972

http://doi.org/10.1631/FITEE.1500293


Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme


Author(s):  Liang Geng, Ji-Zhong Shen, Cong-Yuan Xu

Affiliation(s):  College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   gengliang@zju.edu.cn, jzshen@zju.edu.cn, cyxu@zju.edu.cn

Key Words:  Low power, Flip-flop, Implicit, Clock-gating scheme, Dual-edge


Share this article to: More <<< Previous Article|

Liang Geng , Ji-Zhong Shen , Cong-Yuan Xu . Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(9): 962-972.

@article{title="Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme",
author="Liang Geng , Ji-Zhong Shen , Cong-Yuan Xu ",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="17",
number="9",
pages="962-972",
year="2016",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1500293"
}

%0 Journal Article
%T Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
%A Liang Geng
%A Ji-Zhong Shen
%A Cong-Yuan Xu
%J Frontiers of Information Technology & Electronic Engineering
%V 17
%N 9
%P 962-972
%@ 2095-9184
%D 2016
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1500293

TY - JOUR
T1 - Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
A1 - Liang Geng
A1 - Ji-Zhong Shen
A1 - Cong-Yuan Xu
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 17
IS - 9
SP - 962
EP - 972
%@ 2095-9184
Y1 - 2016
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1500293


Abstract: 
A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.

This manuscript describes a dual-edge implicit pulsed-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS), which employs the transmission-gatelogic-based (TGL) clock gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data keeps unchanged, so the redundant transitions of internal nodes are eliminated and the total power consumption is reduced. This paper has importance in VLSI design particularly in low power application.

采用内嵌时钟控制技术的低功耗双边沿隐形脉冲触发器

概要:本文提出了一种新颖的采用内嵌时钟控制技术的双边沿隐形脉冲触发器(dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme, DIFF-CGS),其在脉冲产生模块中采用了基于时钟控制技术的传输门逻辑。该技术在输入信号不变时关闭反相器链,抑制延迟的时钟信号和锁存器中的冗余跳变,从而降低触发器的功耗。基于SMIC 65 nm工艺的后端仿真结果显示,与相关文献中的同类脉冲型触发器相比,在输入信号开关转换率为10%时,本文提出的DIFF-CGS减少了41.39%–56.21%的功耗。此外,在隐形脉冲发生模块和静态锁存器中节点的全摆幅跳变特性提高了电路的鲁棒性。所以,DIFF-CGS适用于信号转换频率较低的低功耗超大规模集成电路(very-large-scale integration, VLSI)中。
关键词:低功耗;触发器;隐性;时钟控制技术;双边沿

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1]Geng, L., Shen, J.Z., Xu, C.Y., 2016. Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications. IET Comput. Dig. Techn., 10(4):193-201.

[2]Goh, W.L., Yeo, K.S., Zhang, W., et al., 2007. A novel static dual edge-trigger flip-flop for high-frequency low-power application. IEEE Int. Symp. on Integrated Circuits, p.208-211.

[3]Hwang, Y.T., Lin, J.F., Sheu, M.H., 2012. Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme. IEEE Trans. VLSI Syst., 20(2):361-366.

[4]Hyman, R., Ranganathan, N., Bingel, T., et al., 2013. A clock control strategy for peak power and RMS current reduction using path clustering. IEEE Trans. VLSI Syst., 21(2):259-269.

[5]Judy, D.J., Kanchana Bhaaskaran, V.S., 2012. Energy recovery clock-gating scheme and negative edge triggering flip-flop for low power applications. Int. Conf. on Devices, Circuits and Systems, p.140-143.

[6]Kawaguchi, H., Takayasu, S., 1998. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J. Sol.-State Circuit., 33(5):807-811.

[7]Kim, S., Han, I., Paik, S., et al., 2011. Pulser gating: a clock-gating of pulsed-latch circuits. Proc. IEEE Asia South Pacific Design Automation Conf., p.190-195.

[8]Klass, F., Amir, C., Das, A., et al., 1999. A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. IEEE J. Sol.-State Circuit., 34(5):712-716.

[9]Ko, U., Balsara, P.T., 2000. High-performance energy-efficient D-flip-flop circuits. IEEE Trans. VLSI Syst., 8(1):94-98.

[10]Kong, B.S., Kim, S.S., Jun, Y.H., 2001. Conditional-capture flip-flop for statistical power reduction. IEEE J. Solid-State Circuits, 36(8):1263-1271.

[11]Kulkarni, S.H., Sylvester, D., 2004. High performance level conversion for dual VDD design. IEEE Trans. VLSI Syst., 12(9):926-936.

[12]Maxim, A., Gheorghe, M., 2001. A novel physical based model of deep submicron CMOS transistors mismatch for Monte Carlo SPICE simulation. IEEE Int. Symp. on Circuits and Systems, p.511-514.

[13]Nedovic, N., Aleksic, M., Oklobdzija, V.G., 2002. Conditional pre-charge techniques for power-efficient dual-edge clocking. Proc. Int. Symp. on Low Power Electronics and Design, p.56-59.

[14]Phyu, M.W., Fu, K., Goh, W.L., et al., 2011. Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. IEEE Trans. VLSI Syst., 19(1):1-9.

[15]Shen, J.Z., Geng, L., Wu, X.X., 2015. Low power pulse-triggered flip-flop based on clock triggering edge control technique. J. Circuit. Syst. Comput., 24(07):1550094.

[16]Stojanovic, V., Oklobdzija, V.G., 1999. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE J. Sol.-State Circuit., 34(4):536-548.

[17]Strollo, A.G.M., de Caro, D., Napoli, E., et al., 2005. A novel high-speed sense-amplifier-based flip-flop. IEEE Trans. VLSI Syst., 13(11):1266-1274.

[18]Teh, C.K., Hamada, M., Fujita, T., et al., 2006. Conditional data mapping flip-flops for low-power and high-performance systems. IEEE Trans. VLSI Syst., 14(12):1379-1383.

[19]Teh, C.K., Fujita, T., Hara, H., et al., 2011. A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adoptive-coupling configuration in 40nm CMOS. Proc. IEEE Int. Sol.-State Circuit. Conf. on Digest of Technical Papers, p.338-340.

[20]Weste, N.H.E., 2006. CMOS VLSI Design: a Circuits and Systems Perspective (3rd Ed.). Pearson Education, Noida, India.

[21]Wu, Q., Pedram, M., Wu, X., 2000. Clock-gating and its application to low power design of sequential circuits. IEEE Trans. Circuit Syst.-I, 47(3):415-420.

[22]Wu, X.X., Shen, J.Z., 2012. Low-power explicit-pulsed triggered flip-flop with robust output. Electron. Lett., 48(24):1523-1525.

[23]Xiang, G.P., Shen, J.Z., Wu, X.X., et al., 2013. Design of a low-power pulse-triggered flip-flop with conditional clock technique. IEEE Int. Symp. on Circuits and Systems, p.121-124.

[24]Zeitzoff, P.M., Chung, J.E., 2005. A perspective from the 2003 ITRS: MOSFET scaling trends, challenges, and potential solutions. IEEE Circuit. Devic. Mag., 21(1):4-15.

[25]Zhao, P., Darwish, T.K., Bayoumi, M.A., 2004. High-performance and low power conditional discharge flip-flop. IEEE Trans. VLSI Syst., 12(5):477-484.

Open peer comments: Debate/Discuss/Question/Opinion

<1>

Please provide your name, email address and a comment





Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - 2022 Journal of Zhejiang University-SCIENCE