CLC number: TN432
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2016-08-15
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Liang Geng , Ji-Zhong Shen , Cong-Yuan Xu . Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(9): 962-972.
@article{title="Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme",
author="Liang Geng , Ji-Zhong Shen , Cong-Yuan Xu ",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="17",
number="9",
pages="962-972",
year="2016",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1500293"
}
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%T Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
%A Liang Geng
%A Ji-Zhong Shen
%A Cong-Yuan Xu
%J Frontiers of Information Technology & Electronic Engineering
%V 17
%N 9
%P 962-972
%@ 2095-9184
%D 2016
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1500293
TY - JOUR
T1 - Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
A1 - Liang Geng
A1 - Ji-Zhong Shen
A1 - Cong-Yuan Xu
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 17
IS - 9
SP - 962
EP - 972
%@ 2095-9184
Y1 - 2016
PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.1500293
Abstract: A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.
This manuscript describes a dual-edge implicit pulsed-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS), which employs the transmission-gatelogic-based (TGL) clock gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data keeps unchanged, so the redundant transitions of internal nodes are eliminated and the total power consumption is reduced. This paper has importance in VLSI design particularly in low power application.
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