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CLC number: TN47

On-line Access: 2012-03-01

Received: 2011-07-04

Revision Accepted: 2011-10-25

Crosschecked: 2012-02-08

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Journal of Zhejiang University SCIENCE C 2012 Vol.13 No.3 P.232-237

http://doi.org/10.1631/jzus.C1100193


Array based HV/VH tree: an effective data structure for layout representation


Author(s):  Jie Ren, Wei-wei Pan, Yong-jun Zheng, Zheng Shi, Xiao-lang Yan

Affiliation(s):  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   renjie@vlsi.zju.edu.cn, shiz@vlsi.zju.edu.cn

Key Words:  Very large scale integration (VLSI), Layout representation, HV/VH trees, Region query


Jie Ren, Wei-wei Pan, Yong-jun Zheng, Zheng Shi, Xiao-lang Yan. Array based HV/VH tree: an effective data structure for layout representation[J]. Journal of Zhejiang University Science C, 2012, 13(3): 232-237.

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A1 - Jie Ren
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A1 - Xiao-lang Yan
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Abstract: 
We present a new data structure for the representation of an integrated circuit layout. It is a modified HV/VH tree using arrays as the primary container in bisector lists and leaf nodes. By grouping and sorting objects within these arrays together with a customized binary search algorithm, our new data structure provides excellent performance in both memory usage and region query speed. Experimental results show that in comparison with the original HV/VH tree, which has been regarded as the best layout data structure to date, the new data structure uses much less memory and can become 30% faster on region query.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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