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CLC number: TN432

On-line Access: 2011-07-04

Received: 2010-10-22

Revision Accepted: 2011-01-25

Crosschecked: 2011-05-31

Cited: 3

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Journal of Zhejiang University SCIENCE C 2011 Vol.12 No.7 P.604-607


Design of a novel low power 8-transistor 1-bit full adder cell

Author(s):  Yi Wei, Ji-zhong Shen

Affiliation(s):  Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   onlyonewy@126.com, jzshen@zju.edu.cn

Key Words:  Full adder design, Low power, CMOS circuit, Very large-scale integration (VLSI)

Yi Wei, Ji-zhong Shen. Design of a novel low power 8-transistor 1-bit full adder cell[J]. Journal of Zhejiang University Science C, 2011, 12(7): 604-607.

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publisher="Zhejiang University Press & Springer",

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T1 - Design of a novel low power 8-transistor 1-bit full adder cell
A1 - Yi Wei
A1 - Ji-zhong Shen
J0 - Journal of Zhejiang University Science C
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SP - 604
EP - 607
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Y1 - 2011
PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.C1000372

An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper we propose a novel 1-bit full adder cell which uses only eight transistors. In this design, three multiplexers and one inverter are applied to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay, and power-delay produced using the new design are analyzed and compared with those of other designs using HSPICE simulations. The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value. The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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