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On-line Access: 2012-05-03

Received: 2011-08-22

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Journal of Zhejiang University SCIENCE C 2012 Vol.13 No.5 P.376-384


Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process

Author(s):  Jiao-jiao Zhu, Xiao-hua Luo, Li-sheng Chen, Yi Ye, Xiao-lang Yan

Affiliation(s):  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   luoxh@vlsi.zju.edu.cn

Key Words:  Chemical mechanical polishing (CMP), Scratch, Defect, Yield model, Critical area

Jiao-jiao Zhu, Xiao-hua Luo, Li-sheng Chen, Yi Ye, Xiao-lang Yan. Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process[J]. Journal of Zhejiang University Science C, 2012, 13(5): 376-384.

@article{title="Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process",
author="Jiao-jiao Zhu, Xiao-hua Luo, Li-sheng Chen, Yi Ye, Xiao-lang Yan",
journal="Journal of Zhejiang University Science C",
publisher="Zhejiang University Press & Springer",

%0 Journal Article
%T Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process
%A Jiao-jiao Zhu
%A Xiao-hua Luo
%A Li-sheng Chen
%A Yi Ye
%A Xiao-lang Yan
%J Journal of Zhejiang University SCIENCE C
%V 13
%N 5
%P 376-384
%@ 1869-1951
%D 2012
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1100242

T1 - Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process
A1 - Jiao-jiao Zhu
A1 - Xiao-hua Luo
A1 - Li-sheng Chen
A1 - Yi Ye
A1 - Xiao-lang Yan
J0 - Journal of Zhejiang University Science C
VL - 13
IS - 5
SP - 376
EP - 384
%@ 1869-1951
Y1 - 2012
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1100242

In existing integrated circuit (IC) fabrication methods, the yield is typically limited by defects generated in the manufacturing process. In fact, the yield often shows a good correlation with the type and density of the defect. As a result, an accurate defect limited yield model is essential for accurate correlation analysis and yield prediction. Since real defects exhibit a great variety of shapes, to ensure the accuracy of yield prediction, it is necessary to select the most appropriate defect model and to extract the critical area based on the defect model. Considering the realistic outline of scratches introduced by the chemical mechanical polishing (CMP) process, we propose a novel scratch-concerned yield model. A linear model is introduced to model scratches. Based on the linear model, the related critical area extraction algorithm and defect density distribution are discussed. Owing to higher correspondence with the realistic outline of scratches, the linear defect model enables a more accurate yield prediction caused by scratches and results in a more accurate total product yield prediction as compared to the traditional circular model.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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