| index | Title |
| 1 | Design and FPGA verification of a novel reliable real-time data transfer system Author(s):Yu-ping LIAN, Yan HAN, Ming-xu HUO, Jin-long CHEN, Yan ZHANG Clicked:7311 Download:3868 Cited:1 <Full Text> Journal of Zhejiang University Science A 2008 Vol.9 No.10 P.1406-1410 DOI:10.1631/jzus.A0720123 |
| 2 | High-performance hardware architecture of elliptic curve cryptography processor over GF(2163) Author(s):Yong-ping DAN, Xue-cheng ZOU, Zheng-lin LIU, Yu HAN, Li-hua YI Clicked:6321 Download:3948 Cited:5 <Full Text> Journal of Zhejiang University Science A 2009 Vol.10 No.2 P.301-310 DOI:10.1631/jzus.A0820024 |
| 3 | DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers Author(s):GUAN Yun-feng, ZHANG Zhao-yang, Lai Li-feng Clicked:5180 Download:3005 Cited:1 <Full Text> Journal of Zhejiang University Science 2003 Vol.4 No.5 P.526-531 DOI:10.1631/jzus.2003.0526 |
| 4 | A VHDL application for kinematic equation solutions of multi-degree-of-freedom systems Author(s):Hüseyin Oktay Erkol, Hüseyin Demirel Clicked:8524 Download:3622 Cited:1 <Full Text> <PPT> 2581 Journal of Zhejiang University Science C 2014 Vol.15 No.12 P.1164-1173 DOI:10.1631/jzus.C1400120 |
| 5 | Side-channel attacks and learning-vector quantization Author(s):Ehsan Saeedi, Yinan Kong, Md. Selim Hossain Clicked:9158 Download:3348 Cited:0 <Full Text> Frontiers of Information Technology & Electronic Engineering 2017 Vol.18 No.4 P.511-518 DOI:10.1631/FITEE.1500460 |
| 6 | Recent advances in efficient computation of deep convolutional neural networks Author(s):Jian Cheng, Pei-song Wang, Gang Li, Qing-hao Hu, Han-qing Lu Clicked:10473 Download:3668 Cited:0 <Full Text> <PPT> 2313 Frontiers of Information Technology & Electronic Engineering 2018 Vol.19 No.1 P.64-77 DOI:10.1631/FITEE.1700789 |
| 7 | Correlation power attack on a message authentication code based on SM3 Author(s):Ye Yuan, Kai-ge Qu, Li-ji Wu, Jia-wei Ma, Xiang-min Zhang Clicked:8007 Download:2644 Cited:0 <Full Text> <PPT> 1852 Frontiers of Information Technology & Electronic Engineering 2019 Vol.20 No.7 P.930-945 DOI:10.1631/FITEE.1800312 |
| 8 | Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA Author(s):Vijay Dahiphale, Gaurav Bansod, Ankur Zambare, Narayan Pisharoty Clicked:7315 Download:3168 Cited:0 <Full Text> <PPT> 1925 Frontiers of Information Technology & Electronic Engineering 2020 Vol.21 No.4 P.615-628 DOI:10.1631/FITEE.1800681 |
| 9 | Dynamic analysis, FPGA implementation, and cryptographic application of an autonomous 5D chaotic system with offset boosting Author(s):Sifeu Takougang Kingni, Karthikeyan Rajagopal, Serdar Çiçek, Ashokkumar Srinivasan, Anitha Karthikeyan Clicked:8077 Download:7469 Cited:0 <Full Text> Frontiers of Information Technology & Electronic Engineering 2020 Vol.21 No.6 P.950-961 DOI:10.1631/FITEE.1900167 |
