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CLC number: TP183; TN6

On-line Access: 2024-08-27

Received: 2023-10-17

Revision Accepted: 2024-05-08

Crosschecked: 2021-05-08

Cited: 0

Clicked: 4883

Citations:  Bibtex RefMan EndNote GB/T7714

 ORCID:

Yi-fei Pu

https://orcid.org/0000-0003-2975-4976

Qiuyan He

https://orcid.org/0000-0002-4983-778X

Xiao Yuan

https://orcid.org/0000-0003-3003-0326

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Frontiers of Information Technology & Electronic Engineering  2021 Vol.22 No.6 P.862-876

http://doi.org/10.1631/FITEE.2000085


Fractional-order memristive neural synaptic weighting achieved by pulse-based fracmemristor bridge circuit


Author(s):  Yifei Pu, Bo Yu, Qiuyan He, Xiao Yuan

Affiliation(s):  College of Computer Science, Sichuan University, Chengdu 610065, China; more

Corresponding email(s):   heqiuyan789@163.com, yuanxiao@scu.edu.cn

Key Words:  Fractional calculus, Fracmemristor, Fracmemristance, Fractional-order memristor, Fractional-order memristive synapses


Yifei Pu, Bo Yu, Qiuyan He, Xiao Yuan. Fractional-order memristive neural synaptic weighting achieved by pulse-based fracmemristor bridge circuit[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(6): 862-876.

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number="6",
pages="862-876",
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publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2000085"
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%T Fractional-order memristive neural synaptic weighting achieved by pulse-based fracmemristor bridge circuit
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%A Bo Yu
%A Qiuyan He
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%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2000085

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T1 - Fractional-order memristive neural synaptic weighting achieved by pulse-based fracmemristor bridge circuit
A1 - Yifei Pu
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A1 - Xiao Yuan
J0 - Frontiers of Information Technology & Electronic Engineering
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.2000085


Abstract: 
We propose a novel circuit for the fractional-order memristive neural synaptic weighting (FMNSW). The introduced circuit is different from the majority of the previous integer-order approaches and offers important advantages. Since the concept of memristor has been generalized from the classic integer-order memristor to the fractional-order memristor (fracmemristor), a challenging theoretical problem would be whether the fracmemristor can be employed to implement the fractional-order memristive synapses or not. In this research, characteristics of the FMNSW, realized by a pulse-based fracmemristor bridge circuit, are investigated. First, the circuit configuration of the FMNSW is explained using a pulse-based fracmemristor bridge circuit. Second, the mathematical proof of the fractional-order learning capability of the FMNSW is analyzed. Finally, experimental work and analyses of the electrical characteristics of the FMNSW are presented. Strong ability of the FMNSW in explaining the cellular mechanisms that underlie learning and memory, which is superior to the traditional integer-order memristive neural synaptic weighting, is considered a major advantage for the proposed circuit.

基于脉冲分忆抗桥电路的分数阶记忆性神经突触加权

蒲亦非1,余波1,2,何秋燕1,袁晓3
1四川大学计算机学院(软件学院),中国成都市,610065
2成都师范学院物理与工程技术学院,中国成都市,611130
3四川大学电子信息学院,中国成都市,610065
摘要:提出一种新颖的分数阶记忆性神经突触加权电路。与以往大多数整数阶神经突触加权电路不同,该分数阶记忆性神经突触加权电路具有许多重要优点。由于忆阻的概念已从经典的整数阶忆阻推广到分数阶忆阻(分忆抗),分忆抗能否实现分数阶记忆性突触成为一个具有挑战性的理论问题。本文研究利用脉冲分忆抗桥电路实现的分数阶记忆性神经突触加权电路的特点。首先,利用基于脉冲的分忆抗桥电路设计分数阶记忆性神经突触加权电路结构。其次,从数学上证明分数阶记忆性神经突触加权电路的分数阶学习能力。最后,通过实验研究分数阶记忆性神经突触加权电路的电特性。分数阶记忆性神经突触加权电路在解释学习和记忆基础的细胞机制方面具有很强的能力,优于传统的整数阶神经突触加权电路,是该电路的主要优势。

关键词:分数阶微积分;分忆抗;分忆抗值;分数阶忆阻;分数阶记忆性突触

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

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