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CLC number: TN911
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2021-06-08
Cited: 0
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Citations: Bibtex RefMan EndNote GB/T7714
A BCH error correction scheme applied to FPGA with embedded memory
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Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li. A BCH error correction scheme applied to FPGA with embedded memory[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(8): 1127-1139.
@article{title="A BCH error correction scheme applied to FPGA with embedded memory",
author="Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="22",
number="8",
pages="1127-1139",
year="2021",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2000323"
}
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%A Yang Liu
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%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2000323
TY - JOUR
T1 - A BCH error correction scheme applied to FPGA with embedded memory
A1 - Yang Liu
A1 - Jie Li
A1 - Han Wang
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A1 - Kaiqiang Feng
A1 - Jinqiang Li
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 22
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SP - 1127
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%@ 2095-9184
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.2000323
Abstract: Given the potential for bit flipping of data on a memory medium, a high-speed parallel bose–Chaudhuri–Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.
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