Full Text:
<6203>
Summary: 
<1617>
CLC number: TN911
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2021-06-08
Cited: 0
Clicked: 5333
Citations: Bibtex RefMan EndNote GB/T7714
A BCH error correction scheme applied to FPGA with embedded memory
| ||||||||||||||
Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li. A BCH error correction scheme applied to FPGA with embedded memory[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(8): 1127-1139.
@article{title="A BCH error correction scheme applied to FPGA with embedded memory",
author="Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="22",
number="8",
pages="1127-1139",
year="2021",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2000323"
}
%0 Journal Article
%T A BCH error correction scheme applied to FPGA with embedded memory
%A Yang Liu
%A Jie Li
%A Han Wang
%A Debiao Zhang
%A Kaiqiang Feng
%A Jinqiang Li
%J Frontiers of Information Technology & Electronic Engineering
%V 22
%N 8
%P 1127-1139
%@ 2095-9184
%D 2021
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2000323
TY - JOUR
T1 - A BCH error correction scheme applied to FPGA with embedded memory
A1 - Yang Liu
A1 - Jie Li
A1 - Han Wang
A1 - Debiao Zhang
A1 - Kaiqiang Feng
A1 - Jinqiang Li
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 22
IS - 8
SP - 1127
EP - 1139
%@ 2095-9184
Y1 - 2021
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2000323
Abstract: Given the potential for bit flipping of data on a memory medium, a high-speed parallel bose–Chaudhuri–Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.
[1]Ayinala M, Parhi KK, 2011. High-speed parallel architectures for linear feedback shift registers. IEEE Trans Signal Process, 59(9):4459-4469.
[2]Bellorado J, Kavcic A, 2010. Low-complexity soft-decoding algorithms for Reed–Solomon codes—part I: an algebraic soft-in hard-out chase decoder. IEEE Trans Inform Theory, 56(3):945-959.
[3]Berlekamp E, 2015. Algebraic Coding Theory. World Scientific, London, UK.
[4]Cho SG, Kim D, Choi J, et al., 2014. Block-wise concatenated BCH codes for NAND flash memories. IEEE Trans Commun, 62(4):1164-1177.
[5]Hu GH, Sha J, Wang ZF, 2017. High-speed parallel LFSR architectures based on improved state-space transformations. IEEE Trans Very Large Scale Integr Syst, 25(3):1159-1163.
[6]Jung J, Yoo H, Lee Y, et al., 2015. Efficient parallel architecture for linear feedback shift registers. IEEE Trans Circ Syst II, 62(11):1068-1072.
[7]Kim D, Narayanan KR, Ha J, 2018. Symmetric block-wise concatenated BCH codes for NAND flash memories. IEEE Trans Commun, 66(10):4365-4380.
[8]Kim J, Sung W, 2012. Low-energy error correction of NAND flash memory through soft-decision decoding. EURASIP J Adv Signal Process, 2012(1):195.
[9]Kumar HP, Sripati U, Shetty KR, 2012. High-speed and parallel approach for decoding of binary BCH codes with application to flash memory devices. Int J Electron, 99(5):683-693.
[10]Massey J, 1969. Shift-register synthesis and BCH decoding. IEEE Trans Inform Theory, 15(1):122-127.
[11]Moon TK, 2005. Error Correction Coding: Mathematical Methods and Algorithms. John Wiley & Sons, Inc., Hoboken, USA.
[12]Neubauer A, Freudenberger J, Kühn V, 2007. Coding Theory: Algorithms, Architectures, and Applications. John Wiley & Sons, Ltd., Chichester, UK.
[13]Paar C, 1996. A new architecture for a parallel finite field multiplier with low complexity based on composite fields. IEEE Trans Comput, 45(7):856-861.
[14]Pandian KKS, Ray KC, 2015. Five decade evolution of feedback shift register: algorithms, architectures and applications. Int J Commun Netw Distr Syst, 15(2-3):279.
[15]Pei TB, Zukowski C, 1992. High-speed parallel CRC circuits in VLSI. IEEE Trans Commun, 40(4):563-657.
[16]Shieh MD, Sheu MH, Chen CH, et al., 2001. A systematic approach for parallel CRC computations. J Inform Sci Eng, 17(3):445-461.
[17]Unal B, Akoglu A, Ghaffari F, et al., 2018. Hardware implementation and performance analysis of resource efficient probabilistic hard decision LDPC decoders. IEEE Trans Circ Syst I, 65(9):3074-3084.
[18]Xu FX, Liu Y, Liu YQ, et al., 2013. Design and implementation of mode reconfigurable NAND flash error correcting system. J Centr South Univ Sci Technol, 44(5):1918-1925 (in Chinese).
[19]Yang CG, Emre Y, Chakrabarti C, 2012. Product code schemes for error correction in MLC NAND flash memories. IEEE Trans Very Large Scale Integr Syst, 20(12):2302-2314.
[20]Zhang M, Wu F, Xie CS, 2015. A novel optimization algorithm for Chien search of BCH codes in NAND flash memory devices. IEEE Int Conf on Networking, Architecture and Storage, p.106-111.
[21]Zhang XM, 2019. A low-power parallel architecture for linear feedback shift registers. IEEE Trans Circ Syst II, 66(3):412-416.
[22]Zhang XM, Parhi KK, 2005. High-speed architectures for parallel long BCH encoders. IEEE Trans Very Large Scale Integr Syst, 13(7):872-877.
ORCID: 
Open peer comments: Debate/Discuss/Question/Opinion
<1>