Similar articles

Abstract: power integrity (PI) has become a limiting factor for the chip’s overall performance, and how to place in-package decoupling capacitors to improve a chip’s PI performance has become a hot issue. In this paper, we propose an improved transmission matrix method (TMM) for fast decoupling capacitance allocation. An irregular grid partition mechanism is proposed, which helps speed up the impedance computation and complies better with the irregular power/ground (P/G) plane or planes with many vias and decoupling capacitors. Furthermore, we also ameliorate the computation procedure of the impedance matrix whenever decoupling capacitors are inserted or removed at specific ports. With the fast computation of impedance change, in-package decoupling capacitor allocation is done with an efficient change based method in the frequency domain. Experimental results show that our approach can gain about 5× speedup compared with a general TMM, and is efficient in restraining the noise on the P/G plane.

[1] Chen, J., He, L., 2007. Efficient in-package decoupling capacitor optimization for I/O power integrity. IEEE Trans. on Computer-Aided Design Integr. Circuits Syst., 26(4):734-738.

[2] Chen, K.S., 2001. Applied Electromagnetism. Zhejiang University Press, Hangzhou, p.76-109 (in Chinese).

[3] Fang, J., Liu, Y., Chen, Y., Wu, Z., Agrawal, A., 1993. Modeling of power/ground plane noise in high speed digital electronics packaging. Electr. Perform. Electr. Pack., p.206-208.

[4] Kim, J.H., Swaminathan, M., 2001. Modeling of irregular shaped power distribution planes using transmission matrix method. IEEE Trans. on Adv. Pack., 24(3):334-336.

[5] Kim, J.H., Swaminathan, M., 2002. Modeling of multilayered power distribution planes using transmission matrix method. IEEE Trans. on Adv. Pack., 25(2):189-199.

[6] Lee, J., Dragos, M.H., Iyer, M.K., Kim, H., Kim, J., 2005. Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs. Adv. Pack., 28(2):298-309.

[7] Lee, K., Barber, A., 1995. Modeling and analysis of multichip module power supply planes. Comp., Pack., Manufact. Technol., 23(4):628-639.

[8] Li, S.Q., Yu, Y.X., Chan, C.F., Chan, K.F., Tsang, L., 2001. A sparse-matrix/canonical grid method for analyzing densely packed interconnects. IEEE Trans. on Microwave Theory Tech., 49(7):1221-1228.

[9] Na, N., Choi, J., Chun, S., Swaminathan, M., Srinivasan, J., 2000. Modeling and transient simulation of planes in electronic packages. IEEE Trans. on Adv. Pack., 23(3):340-352.

[10] Na, N.J., Budell, T., Chiu, C., Tremble, E., Wemple, I., 2004. The Effects of On-chip and Package Decoupling Capacitors and an Efficient ASIC Decoupling Methodology. Electronic Components and Technology Conf., p.556-567.

[11] Phillips, J.R., White, J.K., 1997. A precorrected-FFT method for electrostatic analysis of complicated 3-D structures. IEEE Trans. on Computer-Aided Design Integr. Circuits Syst., 16(10):1059-1072.

[12] Wang, C., Mao, J.K., Selli, C., Luan, S.F., Zhang, L., Fan, J., Pommerenke, D.J., DuBroff, R.E., Drewniak, J.L., 2006. An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances. IEEE Trans. on Adv. Pack., 29(2):320-334.

[13] Wang, H.G., Chan, C.H., Tsang, L., 2004. A New Multilevel Green’s Function Interpolation Method for Large Scale EM Simulations in RF ICs. IEEE Antennas and Propagation Society Int. Symp., p.1182-1186.

[14] Zheng, H., Pileggi, L.T., 2002. Robust and Passive Model Order Reduction for Circuit Containing Susceptance Elements. IEEE Int. Conf. on Computer Aided Design, p.761-766.

[15] Zheng, H., Krauter, B., Pileggi, L., 2003. On-Package Decoupling Optimization with Package Macromodels. Proc. IEEE Custom Integrated Circuits Conf., p.723-726.