Full Text:   <3677>

CLC number: TN4

On-line Access: 2012-05-03

Received: 2011-08-22

Revision Accepted: 2012-01-06

Crosschecked: 2012-04-09

Cited: 1

Clicked: 6866

Citations:  Bibtex RefMan EndNote GB/T7714

-   Go to

Article info.
Open peer comments

Journal of Zhejiang University SCIENCE C 2012 Vol.13 No.5 P.376-384

http://doi.org/10.1631/jzus.C1100242


Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process


Author(s):  Jiao-jiao Zhu, Xiao-hua Luo, Li-sheng Chen, Yi Ye, Xiao-lang Yan

Affiliation(s):  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   luoxh@vlsi.zju.edu.cn

Key Words:  Chemical mechanical polishing (CMP), Scratch, Defect, Yield model, Critical area


Jiao-jiao Zhu, Xiao-hua Luo, Li-sheng Chen, Yi Ye, Xiao-lang Yan. Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process[J]. Journal of Zhejiang University Science C, 2012, 13(5): 376-384.

@article{title="Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process",
author="Jiao-jiao Zhu, Xiao-hua Luo, Li-sheng Chen, Yi Ye, Xiao-lang Yan",
journal="Journal of Zhejiang University Science C",
volume="13",
number="5",
pages="376-384",
year="2012",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1100242"
}

%0 Journal Article
%T Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process
%A Jiao-jiao Zhu
%A Xiao-hua Luo
%A Li-sheng Chen
%A Yi Ye
%A Xiao-lang Yan
%J Journal of Zhejiang University SCIENCE C
%V 13
%N 5
%P 376-384
%@ 1869-1951
%D 2012
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1100242

TY - JOUR
T1 - Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process
A1 - Jiao-jiao Zhu
A1 - Xiao-hua Luo
A1 - Li-sheng Chen
A1 - Yi Ye
A1 - Xiao-lang Yan
J0 - Journal of Zhejiang University Science C
VL - 13
IS - 5
SP - 376
EP - 384
%@ 1869-1951
Y1 - 2012
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1100242


Abstract: 
In existing integrated circuit (IC) fabrication methods, the yield is typically limited by defects generated in the manufacturing process. In fact, the yield often shows a good correlation with the type and density of the defect. As a result, an accurate defect limited yield model is essential for accurate correlation analysis and yield prediction. Since real defects exhibit a great variety of shapes, to ensure the accuracy of yield prediction, it is necessary to select the most appropriate defect model and to extract the critical area based on the defect model. Considering the realistic outline of scratches introduced by the chemical mechanical polishing (CMP) process, we propose a novel scratch-concerned yield model. A linear model is introduced to model scratches. Based on the linear model, the related critical area extraction algorithm and defect density distribution are discussed. Owing to higher correspondence with the realistic outline of scratches, the linear defect model enables a more accurate yield prediction caused by scratches and results in a more accurate total product yield prediction as compared to the traditional circular model.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

[1]Allan, G.A., Walton, A.J., 1997. Efficient Critical Area Estimation for Arbitrary Defect Shapes. Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, p.20-28.

[2]Allan, G.A., Walton, A.J., 1998. Critical area extraction for soft fault estimation. IEEE Trans. Semicond. Manuf., 11(1):146-154.

[3]Aytes, S.D., Armstrong, J.S., Mortensen, K.A., Mortensen, K.A., Russell, C.W., Ross, K.A., Giraud, J.E., Hooper, D.H., Alexander, H.M., Nelson, M.M., et al., 2003. Experimental Investigation of the Mechanism for CMP Micro-scratch Formation. Proc. 15th Biennial Microelectronics Symp., p.107-109.

[4]Hess, C., Stroele, A.P., 1994. Modeling of real defect outlines and parameter extraction using a checkerboard test structure to localize defects. IEEE Trans. Semicond. Manuf., 7(3):284-292.

[5]Hess, C., Weiland, L.H., 1996. Issues on the Size and Outline of Killer Defects and Their Influence on Yield Modeling. IEEE/SEML Advanced Semiconductor Manufacturing Conf., p.423-428.

[6]Huang, J., Chen, H.C., Wu, J.Y., Lur, W., 1999. Investigation of CMP Micro-Scratch in the Fabrication of Sub-quarter Micron VLSI Circuit. Proc. Chemical Mechanical Polishing–Multilevel of Interconnection Conf., p.77-79.

[7]Jung, S.M., Uom, J.S., Cho, W.S., Bae, Y.J., Chung, Y.K., Yu, K.S., Kim, K.Y., Kim, K.T., 2001. A Study of Formation and Failure Mechanism of CMP Scratch Induced Defects on ILD in a W-damascene Interconnect SRAM Cell. IEEE 39th Annual Int. Reliability Physics Symp., p.42-47.

[8]Khare, J.B., Maly, W., Thomas, M.E., 1994. Extraction of defect size distributions in an IC layer using test structure data. IEEE Trans. Semicond. Manuf., 7(3):354-368.

[9]Lauther, U., 1981. An O(NlogN) Algorithm for Boolean Mask Operations. Proc. 18th Design Automation Conf., p.555-560.

[10]Luo, J.F., Dornfeld, D.A., 2004. Integrated Modeling of Chemical Mechanical Planarization for Sub-micron Integrated Circuit Fabrication. Springer, NY, USA.

[11]Maeda, S., Oka, K., Shibata, Y., Yoshida, M., 2001. Defect Inspection Method and Apparatus. US Patent No. 6169282B1.

[12]May, G.S., Spanos, C.J., 2006. Fundamentals of Semiconductor Manufacturing and Process Control. John Wiley & Sons, Inc., Hoboken, New Jersey.

[13]Ollendorf, H., Cabral, S., Fuller, R., 2004. Reduction of CMP μ-Scratch Induced Metal Shorts by Introduction of a Post CMP Tungsten Plasma Clean Process in a High Volume DRAM Manufacturing Environment. IEEE Advanced Semiconductor Manufacturing Conf. and Workshop, p.5-8.

[14]O′Mahony, M., 1986. Sensory Evaluation of Food: Statistical Methods and Procedures. CRC Press, FL, USA, p.487.

[15]Park, S.W., Kim, S.Y., 2001. Reduction of Micro-defects in the Inter-Metal Dielectrics (IMD) Chemical Mechanical Polishing (CMP) for ULSI Applications. Proc. Int. Symp. on Electrical Insulating Materials, p.63-66.

[16]Press, W.H., Teukolsky, S.A., Vetterling, W.T., Flannery, B.P., 1992. Numerical Recipes in C: the Art of Scientific Computing. Cambridge University Press, Cambridge, UK, p.616.

[17]Shankar, N.G., Zhong, Z.W., 2005. Defect detection on semiconductor wafer surfaces. Microelectron. Eng., 77(3-4):337-346.

[18]Sheng, Z., Xie, S.Q., Pan, C.Y., 2008. Probability Theory and Mathematical Statistics. China Higher Education Press, Beijing, China, p.129-136 (in Chinese).

[19]Skumanich, A., Cai, M.P., 1999. CMP process development based on rapid automatic defect classification. SPIE, 3743:76-88.

[20]Stapper, C.H., 1983. Modeling of integrated circuit defect sensitivities. IBM J. Res. Devel., 27(6):549-557.

[21]Stapper, C.H., 1984. Modeling of defects in integrated circuit photolithographic patterns. IBM J. Res. Devel., 28(4):461-475.

[22]Walker, H., Director, S.W., 1986. VLASIC: a catastrophic fault yield simulator for integrated circuits. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst., 5(4):541-556.

[23]Zimmerman, D.W., 1997. A note on interpretation of the paired-samples t test. J. Educ. Behav. Stat., 22(3):349-360.

Open peer comments: Debate/Discuss/Question/Opinion

<1>

Please provide your name, email address and a comment





Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - 2024 Journal of Zhejiang University-SCIENCE