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CLC number: TN79
On-line Access: 2016-10-08
Received: 2015-07-07
Revision Accepted: 2015-09-24
Crosschecked: 2016-09-20
Cited: 3
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Design and analysis of carbon nanotube FET based quaternary full adders
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Mohammad Hossein Moaiyeri, Shima Sedighiani, Fazel Sharifi, Keivan Navi. Design and analysis of carbon nanotube FET based quaternary full adders[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(10): 1056-1066.
@article{title="Design and analysis of carbon nanotube FET based quaternary full adders",
author="Mohammad Hossein Moaiyeri, Shima Sedighiani, Fazel Sharifi, Keivan Navi",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="17",
number="10",
pages="1056-1066",
year="2016",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1500214"
}
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Abstract: CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.
In this paper two CNTFET based quaternary full adder cells design is proposed. The proposed design uses the unique properties of CNTFETs such as having desired threshold voltage by adjusting the CNT diameters and having same mobility of p-type and n-type devices. The proposed circuits are simulated under various test conditions using Synopsys HSPICE simulator with 32 nm Stanford comprehensive CNTFET model.
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ORCID: 
Open peer comments: Debate/Discuss/Question/Opinion
<1>
Anna Gina Perri@Department of Electrical and Information Engineering, Polytechnic University of Bari, ITALY<annagina.perri@poliba.it>
2016-12-12 18:49:50
Two new CNTFET based quaternary full adder cells are proposed. According to properties of CNTFETs, the design of MVL circuits is easier and efficient compared to using MOSFETs.
The circuits are examined using a HSPICE simulator with a 32 nm CNTFET model.
The simulation results, conducted under various conditions, indicate that the proposed circuits are faster, consume less power, and consequently have a lower energy consumption than the state-of-the-art quaternary full adders.
The paper is well-written and well-organized and clearly delivers the message to the reader. In particular:
1. There are no technical errors and/or inconsistencies.
2. The Statements are clear, as well as the Conclusions.
3. The level of English is good, Figures are adequate and References are current.
According to my opinion, this paper does not need any review and it may be published.
My only suggestion is to add in References the following two papers:
R. Marani, A.G. Perri: “A Comparison of CNTFET Models through the Design of a SRAM Cell”, ECS Journal of Solid State Science and Technology, vol. 5(10), 2016, pp. M118-M126, doi:10.1149/2.0161610jss.
R. Marani, A.G. Perri: “A Simulation Study of Analogue and Logic Circuits with CNTFETs”, ECS Journal of Solid State Science and Technology, vol. 5(6), 2016, pp. M38-M43, doi:10.1149/2.0121605jss.