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On-line Access: 2021-02-01

Received: 2019-11-29

Revision Accepted: 2020-02-21

Crosschecked: 2020-10-27

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Citations:  Bibtex RefMan EndNote GB/T7714


Wei Zou


Daming Ren


Xuecheng Zou


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Frontiers of Information Technology & Electronic Engineering  2021 Vol.22 No.2 P.251-261


A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP

Author(s):  Wei Zou, Daming Ren, Xuecheng Zou

Affiliation(s):  School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China

Corresponding email(s):   weizou@hust.edu.cn, damingren@hust.edu.cn, estxczou@hust.edu.cn

Key Words:  Frequency synthesizer, Charge pump (CP), Voltage-controlled oscillator (VCO), Current mismatch, Phase noise

Wei Zou, Daming Ren, Xuecheng Zou. A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(2): 251-261.

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author="Wei Zou, Daming Ren, Xuecheng Zou",
journal="Frontiers of Information Technology & Electronic Engineering",
publisher="Zhejiang University Press & Springer",

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%T A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP
%A Wei Zou
%A Daming Ren
%A Xuecheng Zou
%J Frontiers of Information Technology & Electronic Engineering
%V 22
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%D 2021
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1900653

T1 - A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP
A1 - Wei Zou
A1 - Daming Ren
A1 - Xuecheng Zou
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 22
IS - 2
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EP - 261
%@ 2095-9184
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.1900653

A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems, in which the scheme adopts low phase noise voltage-controlled oscillators (VCOs) and a charge pump (CP) with reduced current mismatch. VCOs that determine the out-band phase noise of a phase-locked loop (PLL) based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor. A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors. Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs. Fabricated in a TSMC 0.18-µm CMOS process, the prototype operates from 0.20 to 2.43 GHz. The PLL synthesizer achieves an in-band phase noise of −96.8 dBc/Hz and an out-band phase noise of −122.8 dBc/Hz at the 2.43-GHz carrier. The root-mean-square jitter is 1.2 ps under the worst case, and the measured reference spurs are less than −65.3 dBc. The current consumption is 15.2 mA and the die occupies 850 µm×920 µm.

基于优化的压控振荡器和低电流失配电荷泵的0.20—2.43 GHz分数分频频率合成器


摘要:提出一种适用于多标准无线通信系统的0.20—2.43 GHz分数分频频率合成器方案,该方案采用低相位噪声压控振荡器和低电流失配电荷泵。由于压控振荡器的性能决定了锁相环型频率合成器的带外相位噪声,利用自动幅度控制技术和高品质因数的8字型电感对压控振荡器进行优化。为改善电荷泵电流匹配性能以及减小锁相环相位误差,提出一种具有失配抑制结构的电荷泵。通过理论分析,研究了电流失配对锁相环输出性能的影响。采用台积电0.18-μm CMOS工艺,模型输出频率从0.20 GHz变化到2.43 GHz。这一锁相环型频率合成器在2.43 GHz载波时实现的带内相位噪声为−96.8 dBc/Hz,带外相位噪声为−122.8 dBc/Hz。在最坏情况下,均方根抖动为1.2 ps,测量的参考杂散小于−65.3 dBc。消耗电流15.2 mA,芯片面积为850μm×920μm。


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