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CLC number: TN4
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2014-11-09
Cited: 2
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Citations: Bibtex RefMan EndNote GB/T7714
Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology
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Najam Muhammad Amin, Zhi-gong Wang, Zhi-qun Li. Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology[J]. Journal of Zhejiang University Science C, 2014, 15(12): 1190-1199.
@article{title="Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology",
author="Najam Muhammad Amin, Zhi-gong Wang, Zhi-qun Li",
journal="Journal of Zhejiang University Science C",
volume="15",
number="12",
pages="1190-1199",
year="2014",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1400087"
}
%0 Journal Article
%T Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology
%A Najam Muhammad Amin
%A Zhi-gong Wang
%A Zhi-qun Li
%J Journal of Zhejiang University SCIENCE C
%V 15
%N 12
%P 1190-1199
%@ 1869-1951
%D 2014
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1400087
TY - JOUR
T1 - Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology
A1 - Najam Muhammad Amin
A1 - Zhi-gong Wang
A1 - Zhi-qun Li
J0 - Journal of Zhejiang University Science C
VL - 15
IS - 12
SP - 1190
EP - 1199
%@ 1869-1951
Y1 - 2014
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.C1400087
Abstract: We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator (LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency (IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power (LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain (VCG) of 9.8 dB, a double sideband noise figure (DSB-NF) of 11.6 dB, and a linearity in terms of input 1 dB compression point (Pin,1dB) of −13 dBm are measured. The mixer draws a current of 5 mA from a 1.2 V supply dissipating a power of only 6 mW.
This article has been corrected, see doi:10.1631/FITEE.14e0087
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