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CLC number: TN453
On-line Access: 2021-02-01
Received: 2019-11-29
Revision Accepted: 2020-02-21
Crosschecked: 2020-10-27
Cited: 0
Clicked: 4478
Citations: Bibtex RefMan EndNote GB/T7714
https://orcid.org/0000-0002-8683-9880
A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP
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Wei Zou, Daming Ren, Xuecheng Zou. A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(2): 251-261.
@article{title="A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP",
author="Wei Zou, Daming Ren, Xuecheng Zou",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="22",
number="2",
pages="251-261",
year="2021",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1900653"
}
%0 Journal Article
%T A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP
%A Wei Zou
%A Daming Ren
%A Xuecheng Zou
%J Frontiers of Information Technology & Electronic Engineering
%V 22
%N 2
%P 251-261
%@ 2095-9184
%D 2021
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1900653
TY - JOUR
T1 - A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP
A1 - Wei Zou
A1 - Daming Ren
A1 - Xuecheng Zou
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 22
IS - 2
SP - 251
EP - 261
%@ 2095-9184
Y1 - 2021
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.1900653
Abstract: A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems, in which the scheme adopts low phase noise voltage-controlled oscillators (VCOs) and a charge pump (CP) with reduced current mismatch. VCOs that determine the out-band phase noise of a phase-locked loop (PLL) based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor. A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors. Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs. Fabricated in a TSMC 0.18-µm CMOS process, the prototype operates from 0.20 to 2.43 GHz. The PLL synthesizer achieves an in-band phase noise of −96.8 dBc/Hz and an out-band phase noise of −122.8 dBc/Hz at the 2.43-GHz carrier. The root-mean-square jitter is 1.2 ps under the worst case, and the measured reference spurs are less than −65.3 dBc. The current consumption is 15.2 mA and the die occupies 850 µm×920 µm.
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