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Journal of Zhejiang University SCIENCE A 2005 Vol.6 No.6 P.596-600

http://doi.org/10.1631/jzus.2005.A0596


Low power implementation of datapath using regularity


Author(s):  LAI Li-ya, LIU Peng

Affiliation(s):  Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   lailiya@etang.com

Key Words:  Datapath, Low power, Regularity, Relative placement


LAI Li-ya, LIU Peng. Low power implementation of datapath using regularity[J]. Journal of Zhejiang University Science A, 2005, 6(6): 596-600.

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author="LAI Li-ya, LIU Peng",
journal="Journal of Zhejiang University Science A",
volume="6",
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year="2005",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.2005.A0596"
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T1 - Low power implementation of datapath using regularity
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Abstract: 
datapath accounts for a considerable part of power consumption in VLSI circuit design. This paper presents a method for physical implementation of datapath to achieve low power consumption. regularity is a characteristic of datapath and the key of the proposed method, where synthesis is tightly combined with placement to make full use of regularity, so that low power consumption is achieved. In This paper, a new concept of Synthesis In relative placement (SIRP) is given to deal with the semi-regularity in some datapath. Experimental results of a sample circuit validated the proposed method.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article

Reference

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[2] Chaeryung, P., Taewhan, K., Liu, C.L., 1999. An Integrated Approach to Data Path Synthesis for Power Optimization. The 12th Annual IEEE International Conference on ASIC/SOC, Washington, DC, USA, p.125-129.

[3] Chinnery, D.G., Keutzer, K., 2000. Closing the Gap Between ASIC and Custom: An ASIC Perspective. DAC’00, Los Angeles, CA, p.637-642.

[4] Chiou, L.Y., Muhammand, K., Roy, K., 2001. DSP Data Path Synthesis for Low-power Applications. ICASSP’01, Salt Lake City, UT, USA, p.1165-1168.

[5] Chowdhary, A., Gupta, R.K., 2002. A methodology for synthesis of data path circuits. Design & Test of Computers, 19(6):90-100.

[6] Daily, W.J., Chang, A., 2000. The Role of Custom Design in ASIC Chips. DAC’00, Los Angeles, CA, p.643-672.

[7] Kim, N.S., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J.S., Irwin, M.J., Kandemir, M., Narayanan, V., 2003. Leakage current: Moore’s Law meets static power. Computer, 36(12):68-75.

[8] Rabaey, J.M, 1996. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, New Jersey.

[9] Raghunathan, A., Jha, N.K., 1994. Behavioral Synthesis for Low Power Computer Design. ICCD’94, Cambridge, MA, USA, p.318-322.

[10] Reinhardt, M., 2003. Closing the Gap Between ASIC and Full Custom: A Path to Quality Design. The 4th International Symposium on Quality Electronic Design, p.255.

[11] Tao, Y.T., De, M.G., 2000. Data Path Placement with Regularity. ICCAD’00, San Jose, CA, USA, p.264-270.

[12] Wayne, W., 2002. Modern VLSI Design: System-on-Chip Design, 3rd. Prentice-Hall, New Jersey.

[13] Ye, T.T., Chaudhuri, S., Huang, F., Savoj, H., De, M.G., 2002. Physical Synthesis for ASIC Datapath Circuits. ISCAS 2002, Phoenix, USA, p.365-368.

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