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Journal of Zhejiang University SCIENCE A 2007 Vol.8 No.4 P.631-637


Physical design method of MPSoC

Author(s):  LIU Peng, XIA Bing-jie, TENG Zhao-wei

Affiliation(s):  Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Corresponding email(s):   liupeng@isee.zju.edu.cn, icysummer@zju.edu.cn, jovvy@163.com

Key Words:  Physical design, Fast prototyping, Floorplan, Clock tree synthesis (CTS), Power plan, Multiprocessor system-on-chip (MPSoC)

LIU Peng, XIA Bing-jie, TENG Zhao-wei. Physical design method of MPSoC[J]. Journal of Zhejiang University Science A, 2007, 8(4): 631-637.

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journal="Journal of Zhejiang University Science A",
publisher="Zhejiang University Press & Springer",

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%A XIA Bing-jie
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%DOI 10.1631/jzus.2007.A0631

T1 - Physical design method of MPSoC
A1 - LIU Peng
A1 - XIA Bing-jie
A1 - TENG Zhao-wei
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%@ 1673-565X
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PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.2007.A0631

floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel diagonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network containing hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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