CLC number: TN47
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 0000-00-00
Cited: 1
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LIU Peng, XIA Bing-jie, TENG Zhao-wei. Physical design method of MPSoC[J]. Journal of Zhejiang University Science A, 2007, 8(4): 631-637.
@article{title="Physical design method of MPSoC",
author="LIU Peng, XIA Bing-jie, TENG Zhao-wei",
journal="Journal of Zhejiang University Science A",
volume="8",
number="4",
pages="631-637",
year="2007",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.2007.A0631"
}
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%T Physical design method of MPSoC
%A LIU Peng
%A XIA Bing-jie
%A TENG Zhao-wei
%J Journal of Zhejiang University SCIENCE A
%V 8
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%P 631-637
%@ 1673-565X
%D 2007
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.2007.A0631
TY - JOUR
T1 - Physical design method of MPSoC
A1 - LIU Peng
A1 - XIA Bing-jie
A1 - TENG Zhao-wei
J0 - Journal of Zhejiang University Science A
VL - 8
IS - 4
SP - 631
EP - 637
%@ 1673-565X
Y1 - 2007
PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.2007.A0631
Abstract: floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel diagonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network containing hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.
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