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Journal of Zhejiang University SCIENCE C 1998 Vol.-1 No.-1 P.

http://doi.org/10.1631/FITEE.2100287


Introducing scalable 1-bit full adders for designing QCA arithmetic circuits


Author(s):  Hamideh KHAJEHNASIR-JAHROMI, Pooya TORKZADEH, Massoud DOUSTI

Affiliation(s):  Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

Corresponding email(s):   h.khajehnasir@srbiau.ac.ir, p-torkzadeh@srbiau.ac.ir, m_dousti@srbiau.ac.ir

Key Words:  Quantum-dot cellular automata (QCA), Full adder, RCA, Add/Sub circuit, Multiplier


Hamideh KHAJEHNASIR-JAHROMI, Pooya TORKZADEH, Massoud DOUSTI. Introducing scalable 1-bit full adders for designing QCA arithmetic circuits[J]. Frontiers of Information Technology & Electronic Engineering, 1998, -1(-1): .

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Abstract: 
Designing logic circuits using complementary metal-oxide-semiconductor (CMOS) technology at the nano-scale has been faced with various challenges recently. Undesirable leakage currents, the short-effect channel, and high energy dissipation are some of the concerns. quantum-dot cellular automata (QCA) represents an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS. The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder. A low-complexity full adder block is beneficial for developing various intricate structures. This paper represents scalable 1-bit QCA full adder structures based on cells interaction. Our proposed full adders encompass preference aspects of QCA design, such as a low number of cells used, low latency, and small area occupation. Also, the proposed structures have been expanded to larger circuits, including a 4-bit ripple carry adder, a 4-bit ripple borrow subtractor, an add/Sub circuit, and a 2-bit array multiplier. All designs were simulated and verified using QCADesigner-E version 2.2. This tool can estimate the energy dissipation as well as evaluating the performance of the circuits. Simulation results show that the proposed designs are efficient in complexity, area, latency, cost, and energy dissipation.

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