CLC number: TN432
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2011-07-04
Cited: 1
Clicked: 11740
Zhi-hua Ning, Le-nian He. A low drift curvature-compensated bandgap reference with trimming resistive circuit[J]. Journal of Zhejiang University Science C, 2011, 12(8): 698-706.
@article{title="A low drift curvature-compensated bandgap reference with trimming resistive circuit",
author="Zhi-hua Ning, Le-nian He",
journal="Journal of Zhejiang University Science C",
volume="12",
number="8",
pages="698-706",
year="2011",
publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1000440"
}
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%T A low drift curvature-compensated bandgap reference with trimming resistive circuit
%A Zhi-hua Ning
%A Le-nian He
%J Journal of Zhejiang University SCIENCE C
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%N 8
%P 698-706
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%D 2011
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.C1000440
TY - JOUR
T1 - A low drift curvature-compensated bandgap reference with trimming resistive circuit
A1 - Zhi-hua Ning
A1 - Le-nian He
J0 - Journal of Zhejiang University Science C
VL - 12
IS - 8
SP - 698
EP - 706
%@ 1869-1951
Y1 - 2011
PB - Zhejiang University Press & Springer
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DOI - 10.1631/jzus.C1000440
Abstract: A low temperature drift curvature-compensated complementary metal oxide semiconductor (CMOS) bandgap reference is proposed. A dual-differential-pair amplifier was employed to add compensation with a high-order term of TlnT (T is the thermodynamic temperature) to the traditional 1st-order compensated bandgap. To reduce the offset of the amplifier and noise of the bandgap reference, input differential metal oxide semiconductor field-effect transistors (MOSFETs) of large size were used in the amplifier and to keep a low quiescent current, these MOSFETs all work in weak inversion. The voltage reference’s temperature curvature has been further corrected by trimming a switched resistor network. The circuit delivers an output voltage of 3 V with a low dropout regulator (LDO). The chip was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC)’s 0.35-μm CMOS process, and the temperature coefficient (TC) was measured to be only 2.1×10−6/°C over the temperature range of −40–125 °C after trimming. The power supply rejection (PSR) was −100 dB @ DC and the noise was 42 μV (rms) from 0.1 to 10 Hz.
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