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CLC number: TN764
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2018-04-12
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A multistandard and resource-efficient Viterbi decoder for a multimode communication system
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Yi-qi Xie, Zhi-guo Yu, Yang Feng, Lin-na Zhao, Xiao-feng Gu. A multistandard and resource-efficient Viterbi decoder for a multimode communication system[J]. Frontiers of Information Technology & Electronic Engineering, 2018, 19(4): 536-543.
@article{title="A multistandard and resource-efficient Viterbi decoder for a multimode communication system",
author="Yi-qi Xie, Zhi-guo Yu, Yang Feng, Lin-na Zhao, Xiao-feng Gu",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="19",
number="4",
pages="536-543",
year="2018",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1601596"
}
%0 Journal Article
%T A multistandard and resource-efficient Viterbi decoder for a multimode communication system
%A Yi-qi Xie
%A Zhi-guo Yu
%A Yang Feng
%A Lin-na Zhao
%A Xiao-feng Gu
%J Frontiers of Information Technology & Electronic Engineering
%V 19
%N 4
%P 536-543
%@ 2095-9184
%D 2018
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1601596
TY - JOUR
T1 - A multistandard and resource-efficient Viterbi decoder for a multimode communication system
A1 - Yi-qi Xie
A1 - Zhi-guo Yu
A1 - Yang Feng
A1 - Lin-na Zhao
A1 - Xiao-feng Gu
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 19
IS - 4
SP - 536
EP - 543
%@ 2095-9184
Y1 - 2018
PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.1601596
Abstract: We present a novel standard convolutional symbols generator (SCSG) block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters. The SCSG block generates all the states and calculates all the possible standard convolutional symbols corresponding to the states using an iterative approach. The architecture of the Viterbi decoder based on the SCSG reduces resource consumption for recalculating the branch metrics and rearranging the correspondence between branch metrics and transition paths. The proposed architecture supports constraint lengths from 3 to 9, code rates of 1/2, 1/3, and 1/4, and fully optional polynomials. The proposed Viterbi decoder has been implemented on the Xilinx XC7VX485T device with a high throughput of about 200 Mbps and a low resource consumption of 162k logic gates.
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