CLC number: TP391.7
On-line Access: 2025-10-13
Received: 2024-07-21
Revision Accepted: 2025-03-25
Crosschecked: 2025-10-13
Cited: 0
Clicked: 599
Citations: Bibtex RefMan EndNote GB/T7714
Jie YANG, Kai QIAO, Jian CHEN, Chen CHEN, Lixiang GUO, Bin YAN. A review of automatic schematic generation techniques and their application to printed circuit boards[J]. Frontiers of Information Technology & Electronic Engineering, 2025, 26(9): 1534-1550.
@article{title="A review of automatic schematic generation techniques and their application to printed circuit boards",
author="Jie YANG, Kai QIAO, Jian CHEN, Chen CHEN, Lixiang GUO, Bin YAN",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="26",
number="9",
pages="1534-1550",
year="2025",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2400612"
}
%0 Journal Article
%T A review of automatic schematic generation techniques and their application to printed circuit boards
%A Jie YANG
%A Kai QIAO
%A Jian CHEN
%A Chen CHEN
%A Lixiang GUO
%A Bin YAN
%J Frontiers of Information Technology & Electronic Engineering
%V 26
%N 9
%P 1534-1550
%@ 2095-9184
%D 2025
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2400612
TY - JOUR
T1 - A review of automatic schematic generation techniques and their application to printed circuit boards
A1 - Jie YANG
A1 - Kai QIAO
A1 - Jian CHEN
A1 - Chen CHEN
A1 - Lixiang GUO
A1 - Bin YAN
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 26
IS - 9
SP - 1534
EP - 1550
%@ 2095-9184
Y1 - 2025
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2400612
Abstract: The printed circuit board (PCB) stands as the cornerstone of electronic equipment, with its schematic holding paramount importance for system performance and reliability. In light of the pervasive use of electronic devices in society, concerns regarding maintenance, safety, backdoors, and other latent issues have garnered significant attention. automatic schematic generation (ASG), with its distinct capability for generating circuit schematics autonomously, not only plays a pivotal role in electronic design automation (EDA) but also aids in deciphering the fundamental principles of PCB equipment to effectively address these underlying issues. However, constrained by the increasingly sophisticated manufacturing processes of PCBs and the inherent legal and ethical controversies surrounding reverse engineering, the development of related technologies faces notable bottlenecks. To break through technical barriers and advance technological progress, this paper comprehensively combs through the existing ASG, offers in-depth description of the core algorithms of the technology—layout and routing, and for the application of the technology in PCB reverse engineering, analyzes in detail the current challenges and the faced problems. Around these challenges, feasible solutions are discussed in this paper, with the aims of promoting the research of automatic PCB schematic generation technology and contributing new strength to EDA and PCB reverse engineering automation.
[1]Abel LC, 1972. On the ordering of connections for automatic wire routing. IEEE Trans Comput, C-21(11):1227-1233.
[2]Agnesina A, Chang K, Lim SK, 2020. VLSI placement parameter optimization using deep reinforcement learning. Proc IEEE/ACM Int Conf on Computer-Aided Design, p.1-9.
[3]Arsintescu BG, 1996. A method for analog circuits visualization. Proc Int Conf on Computer Design. VLSI in Computers and Processors, p.454-459.
[4]Botero UJ, Wilson R, Lu HW, et al., 2020. Hardware trust and assurance through reverse engineering: a survey and outlook from image analysis and machine learning perspectives.
[5]Cheng RY, Yan JC, 2021. On joint learning for solving placement and routing in chip design. Proc 35th Int Conf on Neural Information Processing Systems, Article 1262.
[6]Chu C, Wong YC, 2008. FLUTE: fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design. IEEE Trans Computer-Aided Des Integr Circ Syst, 27(1):70-83.
[7]Du XB, Wang CH, Zhong RZ, et al., 2023. HubRouter: learning global routing via hub generation and pin-hub connection. Proc 37th Int Conf on Neural Information Processing Systems, Article 3435.
[8]Frezza ST, Levitan SP, 1993. SPAR: a schematic place and route system. IEEE Trans Computer-Aided Des Integr Circ Syst, 12(7):956-973.
[9]Fu RL, Zhang ZM, Tang GM, et al., 2020. Design automation methodology from RTL to gate-level netlist and schematic for RSFQ logic circuits. Proc Great Lakes Symp on VLSI, p.145-150.
[10]Garg B, Agrawal A, Sehgal R, et al., 2008. Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist. Proc IEEE East-West Design & Test Symp, p.379-382.
[11]Goldie A, Mirhoseini A, 2020. Placement optimization with deep reinforcement learning. Proc Int Symp on Physical Design, p.3-7.
[12]Hanan M, 1966. On Steiner’s problem with rectilinear distance. SIAM J Appl Math, 14(2):255-265.
[13]Hart PE, Nilsson NJ, Raphael B, 1968. A formal basis for the heuristic determination of minimum cost paths. IEEE Trans Syst Sci Cybern, 4(2):100-107.
[14]Hong XN, Lin T, Shi YQ, et al., 2023. GraphClusNet: a hierarchical graph neural network for recovered circuit netlist partitioning. IEEE Trans Artif Intell, 4(5):1199-1213.
[15]Hsu HY, Lin MPH, 2022. Automatic analog schematic diagram generation based on building block classification and reinforcement learning. Proc ACM/IEEE 4th Workshop on Machine Learning for CAD, p.43-48.
[16]Jehng YS, Chen LG, Parng TM, 1991. ASG: automatic schematic generator. Integration, 11(1):11-27.
[17]Jumper J, Evans R, Pritzel A, et al., 2021. Highly accurate protein structure prediction with AlphaFold. Nature, 596(7873):583-589.
[18]Kastner R, Bozorgzadeh E, Sarrafzadeh M, 2000. Predictable routing. IEEE/ACM Int Conf on Computer-Aided Design, p.110-113.
[19]Katsuki K, Shin D, Onizawa N, et al., 2022. Fast solving complete 2000-node optimization using stochastic-computing simulated annealing. 29th IEEE Int Conf on Electronics, Circuits and Systems, p.1-4.
[20]Kim NH, Kim KS, Choi KM, et al., 2000. RightTopologizer: an efficient schematic generator for multi-level optimization. Proc 13th Annual IEEE Int ASIC/SOC Conf, p.387-391.
[21]Lageweg CR, 1998. Designing an Automatic Schematic Generator for a Netlist Description. Technical Report No. 1-68340-44(1998)03, Laboratory of Computer Architecture and Digital Techniques, Delft University of Technology, Delft, the Netherlands.
[22]Lai Y, Liu JX, Tang ZT, et al., 2023. ChiPFormer: transferable chip placement via offline decision transformer. Proc 40th Int Conf on Machine Learning, Article 757.
[23]Lee TD, McNamee LP, 1989. Structure optimization in logic schematic generation. IEEE Int Conf on Computer-Aided Design Digest of Technical Papers, p.330-333.
[24]Lee TD, McNamee LP, 1992. Aesthetic routing for transistor schematics. IEEE/ACM Int Conf on Computer-Aided Design, p.35-38.
[25]Liao HG, Zhang WT, Dong XL, et al., 2020. A deep reinforcement learning approach for global routing. J Mech Des, 142(6):061701.
[26]Mata RC, Azmib S, Daudc R, et al., 2006. Reverse engineering for obsolete single layer printed circuit board (PCB). Int Conf on Computing & Informatics, p.1-7.
[27]Meng D, Zheng YL, 2022. Circuit partitioning for PCB netlist based on net attributes. Int Conf on Machine Learning and Cybernetics, p.31-36.
[28]Mnih V, Kavukcuoglu K, Silver D, et al., 2013. Playing Atari with deep reinforcement learning.
[29]Ou HC, Chien HCC, Chang YW, 2014. Nonuniform multilevel analog routing with matching constraints. IEEE Trans Computer-Aided Des Integr Circ Syst, 33(12):1942-1954.
[30]Rematska G, Bourbakis NG, 2016. A survey on reverse engineering of technical diagrams. 7th Int Conf on Information, Intelligence, Systems & Applications, p.1-8.
[31]Roy R, Raiman J, Kant N, et al., 2021. PrefixRL: optimization of parallel prefix circuits using deep reinforcement learning. 58th ACM/IEEE Design Automation Conf, p.853-858.
[32]Sechen C, 1988. VLSI Placement and Global Routing Using Simulated Annealing. Springer, New York, USA, p.181-243.
[33]Sergey G, Daniil Z, Rustam C, 2019. Simulated annealing based placement optimization for reconfigurable systems-on-chip. IEEE Conf of Russian Young Researchers in Electrical and Electronic Engineering, p.1597-1600.
[34]Sharma A, Dyrkolbotn GO, Overlier L, et al., 2022. A state-of-the-art reverse engineering approach for combating hardware security vulnerabilities at the system and PCB level in IoT devices. IEEE Physical Assurance and Inspection of Electronics, p.1-7.
[35]Shi YQ, Xue K, Lei S, et al., 2023. Macro placement by wire-mask-guided black-box optimization. Proc 37th Int Conf on Neural Information Processing Systems, Article 299.
[36]Steinbrunn M, Moerkotte G, Kemper A, 1997. Heuristic and randomized optimization for the join ordering problem. VLDB J, 6(3):191-208.
[37]Stok L, Koster GP, 1989. From network to artwork. Proc 26th ACM/IEEE Design Automation Conf, p.686-689.
[38]Swinkels GM, Hafer L, 1990. Schematic generation with an expert system. IEEE Trans Computer-Aided Des Integr Circ Syst, 9(12):1289-1306.
[39]Tehranipoor M, Koushanfar F, 2010. A survey of hardware Trojan taxonomy and detection. IEEE Des Test Comput, 27(1):10-25.
[40]Vashisht D, Rampal H, Liao HG, et al., 2020. Placement in integrated circuits using cyclic reinforcement learning and simulated annealing.
[41]Wang HR, Wang K, Yang JC, et al., 2020. GCN-RL circuit designer: transferable transistor sizing with graph neural networks and reinforcement learning. 57th ACM/IEEE Design Automation Conf, p.1-6.
[42]Wu CY, Graeb H, Hu J, 2015. A pre-search assisted ILP approach to analog integrated circuit routing. 33rd IEEE Int Conf on Computer Design, p.244-250.
[43]Wu YP, 2009. Novel method of analog circuit schematic synthesis. IEEE 8th Int Conf on ASIC, p.1209-1212.
[44]Yang J, Qiao K, Shi SH, et al., 2024. AEM-PCB reverser: circuit schematic generation in PCB reverse engineering using reinforcement learning based on aesthetic evaluation metric. IEEE Trans Computer-Aided Des Integr Circ Syst, 43(5):1608-1612.
[45]Zhong RZ, Du XB, Kai SX, et al., 2024a. FlexPlanner: flexible 3D floorplanning via deep reinforcement learning in hybrid action space with multi-modality representation. Proc 38th Int Conf on Neural Information Processing Systems, p.49252-49278.
[46]Zhong RZ, Ye JJ, Tang ZT, et al., 2024b. PreRoutGNN for timing prediction with order preserving partition: global circuit pre-training, local delay learning and attentional cell modeling. Proc 38th AAAI Conf on Artificial Intelligence, p.17087-17095.
Open peer comments: Debate/Discuss/Question/Opinion
<1>