Full Text:
<76>
CLC number:
On-line Access: 2025-03-14
Received: 2024-09-21
Revision Accepted: 2025-01-24
Crosschecked: 0000-00-00
Cited: 0
Clicked: 68
SAPER-AI accelerator: systolic array based power-efficient reconfigurable AI accelerator
| |||||||||||||
Fahad bin MUSLIM†‡1 , Kashif INAYAT† 2, Muhammad zain SIDDIQI†1 , Safiullah KHAN3,Tayyeb MAHMOOD4 , Ihtesham ul ISLAM5. SAPER-AI accelerator: systolic array based power-efficient reconfigurable AI accelerator[J]. Frontiers of Information Technology & Electronic Engineering, 1998, -1(-1): .
@article{title="SAPER-AI accelerator: systolic array based power-efficient reconfigurable AI accelerator",
author="Fahad bin MUSLIM†‡1 , Kashif INAYAT† 2, Muhammad zain SIDDIQI†1 , Safiullah KHAN3,Tayyeb MAHMOOD4 , Ihtesham ul ISLAM5",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="-1",
number="-1",
pages="",
year="1998",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2400867"
}
%0 Journal Article
%T SAPER-AI accelerator: systolic array based power-efficient reconfigurable AI accelerator
%A Fahad bin MUSLIM†‡1
%A Kashif INAYAT† 2
%A Muhammad zain SIDDIQI†1
%A Safiullah KHAN3
%A Tayyeb MAHMOOD4
%A Ihtesham ul ISLAM5
%J Journal of Zhejiang University SCIENCE C
%V -1
%N -1
%P
%@ 2095-9184
%D 1998
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2400867
TY - JOUR
T1 - SAPER-AI accelerator: systolic array based power-efficient reconfigurable AI accelerator
A1 - Fahad bin MUSLIM†‡1
A1 - Kashif INAYAT† 2
A1 - Muhammad zain SIDDIQI†1
A1 - Safiullah KHAN3
A1 - Tayyeb MAHMOOD4
A1 - Ihtesham ul ISLAM5
J0 - Journal of Zhejiang University Science C
VL - -1
IS - -1
SP -
EP -
%@ 2095-9184
Y1 - 1998
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2400867
Abstract: Deep learning (DL) accelerators are critical for handling the growing computational demands of modern neural networks. Systolic array (SA) based accelerators consist of a 2D mesh of processing elements (PE) working cooperatively to accelerate matrix multiplication, a fundamental operation in DL. The power efficiency of such accelerators is of primary importance especially considering the edge AI regime. This work presents the SAPER-AI accelerator, an SA accelerator with power intent specified via a unified power format representation in a simplified manner with negligible micro-architectural optimization effort. Our proposed accelerator switches off rows and columns of PEs in a coarse-grained manner, thus leading to SA micro-architecture complying with the varying computational requirements of modern DL workloads. Our analysis demonstrates enhanced power efficiency ranging between 11% and 25% for the best case 32×32 and 64×64 SA designs, respectively. Additionally, the power delay product (PDP) exhibited a progressive improvement of around 6% for larger SA sizes. Moreover, a performance comparison between the MobileNet and ResNet50 models indicated generally better SA performance for the ResNet50 workload. This is due to the more regular convolutions portrayed by ResNet50 that are more favored by SAs, with the performance gap widening as the SA size increases.
Open peer comments: Debate/Discuss/Question/Opinion
<1>