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Abstract: This paper presents a macroblock-level (MB-level) decoding and deblocking method for supporting the flexible macroblock ordering (FMO) and arbitrary slice ordering (ASO) bit streams in H.264 decoder and its SOC/ASIC implementation. By searching the slice containing the current macroblock in the bit stream and switching slices correctly, MBs can be decoded in the raster scan order, while the decoding process can immediately begin as long as the slice containing the current MB is available. This architectural modification enables the MB-level decoding and deblocking 3-stage pipeline, and saves about 20% of SDRAM bandwidth. Implementation results showed that the design achieves real-time decoding of 1080HD (1920×1088@30 fps) at a system clock of 166 MHz.

[1] Chen, T.W., Huang, Y.W., Chen, T.C., Chen, Y.H., Tsai, C.Y., Chen, L.G., 2005. Architecture Design of H.264/AVC Decoder with Hybrid Task Pipelining for High Definition Videos. IEEE International Symposium on Circuits and Systems. Kobe, Japan, p.2931-2934.

[2] Ha, V.H.S., Choi, S.K., Jeon, J.G., Lee, G.H., Jang, W.K., Shim, W.S., 2004. Real-Time Audio/Video Decoders for Digital Multimedia Broadcasting. The 4th IEEE International Workshop on System-on-Chip for Real-Time Applications. Banff, Alberta, Canada, p.162-167.

[3] Iverson, V., McVeigh, J., Reese, B., 2004. Real-Time H.264-AVC Codec on Intel Architectures. IEEE International Conference on Image Processing. Singapore, p.757-760.

[4] Kang, H.Y., Jeong, K.A., Bae, J.Y., Lee, Y.S., Lee, S.H., 2004. MPEG4 AVC/H.264 Decoder with Scalable Bus Architecture and Dual Memory Controller. Proceedings of the 2004 International Symposium on Circuits and Systems. Vancouver, Canada, p.II-145-148.

[5] Khan, M.O., Khan, U., Rahim, S.A., Ali, S.I., 2004. Optimization of Motion Compensation for H.264 Decoder by Pre-calculation. The 8th IEEE International Multitopic Conference. Lahore, Pakistan, p.55-60.

[6] Lee, J., Moon, S., Sung, W., 2004. H.264 Decoder Optimization Exploiting SIMD Instructions. IEEE Asia-Pacific Conference on Circuits and Systems. Tainan, Taiwan, p.1149-1152.

[7] Lee, S.H., Park, J.H., Kim, S.W., Ko, S.J., Kim, S., 2006. Implementation of H.264/AVC Decoder for Mobile Video Applications. IEEE Asia and South Pacific Conference on Design Automation. Yokohama, Japan, p.120-121.

[8] Park, S., Cho, H., Jung, H., Lee, D., 2005. An Implemented of H.264 Video Decoder Using Hardware and Software. IEEE Custom Integrated Circuits Conference. San Jose, CA, USA, p.271-275.

[9] Ramadurai, V., Jinturkar, S., Moudgill, M., Glossner, J., 2005. Implementation of H.264 Decoder on Sandblaster DSP. IEEE International Conference on Multimedia and Expo. Amsterdam, Netherlands.

[10] Wenger, S., Horowitz, M., 2002a. FMO: Flexible Macroblock Ordering, JVT-C089. Joint Video Team (JVT) 3rd Meeting. Virginia, USA.

[11] Wenger, S., Horowitz, M., 2002b. FMO 101, JVT-D063. Joint Video Team (JVT) 4th Meeting. Klagenfurt, Austria.

[12] Wiegand, T., Sullivan, G.J., Bjntegaard, G., Luthra, A., 2003. Overview of the H.264/AVC video coding standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7):560-576.