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CLC number: TN402

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Received: 2007-12-12

Revision Accepted: 2008-04-24

Crosschecked: 2008-11-16

Cited: 1

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Citations:  Bibtex RefMan EndNote GB/T7714

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Journal of Zhejiang University SCIENCE A 2008 Vol.9 No.12 P.1708-1714


A low-power high-throughput link splitting router for NoCs

Author(s):  Mohsen SANEEI, Ali AFZALI-KUSHA, Zainalabedin NAVABI

Affiliation(s):  Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran

Corresponding email(s):   msaneei@ut.ac.ir, afzali@ut.ac.ir, navabi@cad.ece.ut.ac.ir

Key Words:  Low-power, Latency, Throughput, Network on chip (NoC), Delay-insensitive, Router

Mohsen SANEEI, Ali AFZALI-KUSHA, Zainalabedin NAVABI. A low-power high-throughput link splitting router for NoCs[J]. Journal of Zhejiang University Science A, 2008, 9(12): 1708-1714.

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In this paper, we propose a technique for lowering the latency of the communication in a NoC (network on chip). The technique, which can support two qualities of service (QoS), i.e., the guaranteed throughput (GT) and best effort (BE), is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the 1-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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