Full Text:   <2517>

CLC number: TN402

On-line Access: 

Received: 2007-12-12

Revision Accepted: 2008-04-24

Crosschecked: 2008-11-16

Cited: 1

Clicked: 5006

Citations:  Bibtex RefMan EndNote GB/T7714

-   Go to

Article info.
Open peer comments

Journal of Zhejiang University SCIENCE A 2008 Vol.9 No.12 P.1708-1714


A low-power high-throughput link splitting router for NoCs

Author(s):  Mohsen SANEEI, Ali AFZALI-KUSHA, Zainalabedin NAVABI

Affiliation(s):  Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran

Corresponding email(s):   msaneei@ut.ac.ir, afzali@ut.ac.ir, navabi@cad.ece.ut.ac.ir

Key Words:  Low-power, Latency, Throughput, Network on chip (NoC), Delay-insensitive, Router

Mohsen SANEEI, Ali AFZALI-KUSHA, Zainalabedin NAVABI. A low-power high-throughput link splitting router for NoCs[J]. Journal of Zhejiang University Science A, 2008, 9(12): 1708-1714.

@article{title="A low-power high-throughput link splitting router for NoCs",
author="Mohsen SANEEI, Ali AFZALI-KUSHA, Zainalabedin NAVABI",
journal="Journal of Zhejiang University Science A",
publisher="Zhejiang University Press & Springer",

%0 Journal Article
%T A low-power high-throughput link splitting router for NoCs
%A Mohsen SANEEI
%A Zainalabedin NAVABI
%J Journal of Zhejiang University SCIENCE A
%V 9
%N 12
%P 1708-1714
%@ 1673-565X
%D 2008
%I Zhejiang University Press & Springer
%DOI 10.1631/jzus.A0720117

T1 - A low-power high-throughput link splitting router for NoCs
A1 - Mohsen SANEEI
A1 - Zainalabedin NAVABI
J0 - Journal of Zhejiang University Science A
VL - 9
IS - 12
SP - 1708
EP - 1714
%@ 1673-565X
Y1 - 2008
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/jzus.A0720117

In this paper, we propose a technique for lowering the latency of the communication in a NoC (network on chip). The technique, which can support two qualities of service (QoS), i.e., the guaranteed throughput (GT) and best effort (BE), is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the 1-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.

Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


[1] Benini, L., de Micheli, G., 2002. Network on chips: a new SoC paradigm. IEEE Computer, 35(1):70-78.

[2] Bertozzi, D., Benini, L., 2004. Xpipes: a network-on-chip architecture for gigascale systems-on-chip. IEEE Circuts Syst. Mag., 4(2):18-31.

[3] Davis, J., Meindl, D., 2000. Compact distributed RLC interconnect models—Part II: coupled line transient expressions and peak crosstalk in multilevel networks. IEEE Trans. on Electr. Dev., 47(11):2078-2087.

[4] Im, S., Srivastava, N., Banerjee, K., Goodson, K.E., 2005. Scaling analysis of multilevel interconnect temperatures for high-performance ICs. IEEE Trans. on Electr. Dev., 52(12):2710-2719.

[5] Kim, M., Kim, D., Sobelman, G.E., 2006. Network-on-Chip Link Analysis under Power and Performance Constraints. Proc. Design Automation and Test in Europe Conf. and Exhibition, Island of Kos, Greece, p.4163-4166.

[6] Millberg, M., Nilsson, E., Thid, R., Jantsch, A., 2004. Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. Proc. Conf. on Design, Automation and Test in Europe, Paris, France, p.890-895.

[7] Nigussie, E., Lehtonen, T., Tuuna, S., Plosila, J., Isoaho, J., 2007. High-performance long NoC link using delay-insensitive current-mode signaling. VLSI Design, p.1-13.

[8] Rijpkema, E., Goossens, K., Radulescu, A., Dielissen, J., Meerbergen, J.V., Wielage, P., Waterlander, E., 2003. Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip. IEE Proc.-Comput. Digit. Tech., 150(5):294-302.

[9] Saneei, M., Afzali-Kusha, A., Navabi, Z., 2006. A Mesochronous Technique for Communication in Network on Chips. Proc. 18th Int. Conf. on Micro-electronics, Saudi Arabia, p.32-35.

[10] Santi, S., Lin, B., Kocarev, L., Maggio, G.M., Rovatti, R., Setti, G., 2005. On the Impact of Traffic Statistics on Quality of Service for Networks on Chip. IEEE Int. Symp. on Circuits and Systems, Kobe, Japan, p.2349-2352.

[11] Vellanki, P., Banerjee, N., Chatha, K.S., 2005. Quality-of-service and error control techniques for mesh-based network-on-chip architectures. Integr., VLSI J., 38(3):353-382.

[12] Verhoeff, T., 1988. Delay-insensitive codes—an overview. Distrib. Comput., 3(1):1-8.

Open peer comments: Debate/Discuss/Question/Opinion


Please provide your name, email address and a comment

Journal of Zhejiang University-SCIENCE, 38 Zheda Road, Hangzhou 310027, China
Tel: +86-571-87952783; E-mail: cjzhang@zju.edu.cn
Copyright © 2000 - 2022 Journal of Zhejiang University-SCIENCE