CLC number: TN95
On-line Access: 2024-11-08
Received: 2024-04-08
Revision Accepted: 2024-06-03
Crosschecked: 2024-11-08
Cited: 0
Clicked: 593
Citations: Bibtex RefMan EndNote GB/T7714
Fangjun LIU, Jiaming SHEN, Jizhong SHEN. Research on electromagnetic interference resistance performance of three kinds of CMOS inverters[J]. Frontiers of Information Technology & Electronic Engineering, 2024, 25(10): 1390-1405.
@article{title="Research on electromagnetic interference resistance performance of three kinds of CMOS inverters",
author="Fangjun LIU, Jiaming SHEN, Jizhong SHEN",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="25",
number="10",
pages="1390-1405",
year="2024",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2400264"
}
%0 Journal Article
%T Research on electromagnetic interference resistance performance of three kinds of CMOS inverters
%A Fangjun LIU
%A Jiaming SHEN
%A Jizhong SHEN
%J Frontiers of Information Technology & Electronic Engineering
%V 25
%N 10
%P 1390-1405
%@ 2095-9184
%D 2024
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2400264
TY - JOUR
T1 - Research on electromagnetic interference resistance performance of three kinds of CMOS inverters
A1 - Fangjun LIU
A1 - Jiaming SHEN
A1 - Jizhong SHEN
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 25
IS - 10
SP - 1390
EP - 1405
%@ 2095-9184
Y1 - 2024
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2400264
Abstract: The performance of complementary metal oxide semiconductor (CMOS) circuits is affected by electromagnetic interference (EMI), and the study of the circuit’s ability to resist EMI will facilitate the design of circuits with better performance. current-mode CMOS circuits have been continuously developed in recent years due to their advantages of high speed and low power consumption over conventional circuits under the deep submicron process; their EMI resistance performance deserves further study. This paper introduces three kinds of NOT gate circuits: conventional voltage-mode CMOS, MOS current-mode logic (MCML) with voltage signal of input and output, and current-mode CMOS with current signal of input and output. The effects of EMI on three NOT gate circuits are investigated using Cadence Virtuoso software simulation, and a disturbance level factor is defined to compare the effects of different interference terminals, interference signals’ waveforms, and interference signals’ frequencies on the circuits in the 65 nm process. The relationship between input resistance and circuit EMI resistance performance is investigated by varying the value of cascade resistance at the input of the current-mode CMOS circuits. Simulation results show that the current-mode CMOS circuits have better resistance performance to EMI at high operating frequencies, and the higher the operating frequency of the current-mode CMOS circuits, the better the resistance performance of the circuits to EMI. Additionally, the effects of different temperatures and different processes on the resistance performance of three circuits are also studied. In the temperature range of -40 °C to 125 °C, the higher the temperature, the weaker the resistance ability of voltage-mode CMOS and MCML circuits, and the stronger the resistance ability of current-mode CMOS circuits. In the 28 nm process, the current-mode CMOS circuit interference resistance ability is relatively stronger than that of the other two kinds of circuits. The relative interference resistance ability of voltage-mode CMOS and MCML circuits in the 28 nm process is similar to that of the 65 nm process, while the relative interference resistance ability of current-mode CMOS circuits in the 28 nm process is stronger than that of the 65 nm process. This study provides a basis for the design of current-mode CMOS circuits against EMI.
[1]Albertson RT, Arthur J, Rashid MH, 2006. Overview of electromagnetic interference. 38th North American Power Symp, p.263-266.
[2]Backstrom MG, Lovstrand KG, 2004. Susceptibility of electronic systems to high-power microwaves: summary of test experience. IEEE Trans Electromagn Compat, 46(3):396-403.
[3]Choudhary MS, Pudi NSAK, Redouté JM, et al., 2021. A methodology to emulate the effect of EMI in circuit simulators for wireline communication channel. IEEE Lett Electromagn Compat Pract Appl, 3(3):96-100.
[4]Deutschmann B, Winkler G, 2023. Characterizing the electromagnetic immunity of operational amplifiers based on EMIRR and DPI. Int Symp on Electromagnetic Compatibility-EMC Europe, p.1-4.
[5]Gupta P, Banerjee R, Sharma R, 2021. Low-voltage low-power CMOS-based current-mode implementation of digital logic gates and combinational circuits. J Circ Syst Comput, 30(12):>2150212>.
[6]Hassan H, Anis M, Elmasry M, 2005. MOS current mode circuits: analysis, design, and variability. IEEE Trans Very Large Scale Integr (VLSI) Syst, 13(8):885-898.
[7]Hu Y, Wang ZY, Chen H, et al., 2023. Research on radar jamming for detection performance. J Phys Conf Ser, 2517:012015.
[8]Kim K, Iliadis AA, 2007a. Critical bit errors in CMOS digital inverters due to pulsed electromagnetic interference. Int Conf on Electromagnetics in Advanced Applications, p.217-220.
[9]Kim K, Iliadis AA, 2007b. Critical upsets of CMOS inverters in static operation due to high-power microwave interference. IEEE Trans Electromagn Compat, 49(4):876-885.
[10]Liang B, Ma K, Ding Z, et al., 2012. The structure design of MOS current mode logic adder. Int Conf on Microwave and Millimeter Wave Technology, p.1-4.
[11]Lin JF, Chen YN, Zhao DY, et al., 2021. Simulation analysis of the influence of electromagnetic pulse power on the performance degradation of CMOS inverter. CIE Int Conf on Radar, p.1959-1962.
[12]Mu J, Jia X, 2021. Simulation and analysis of the influence of artificial interference signal style on wireless security system performance. IEEE 4th Advanced Information Management, Communicates, Electronic and Automation Control Conf, p.2106-2109.
[13]Powell T, Sule NH, Hemmady S, et al., 2018. Predictive model for extreme electromagnetic compatibility on CMOS inverters. Int Symp on Electromagnetic Compatibility, p.113-116.
[14]Radasky WA, Baum CE, Wik MW, 2004. Introduction to the special issue on high-power electromagnetics (HPEM) and intentional electromagnetic interference (IEMI). IEEE Trans Electromagn Compat, 46(3):314-321.
[15]Razavi B, 2000. Design of Analog CMOS Integrated Circuits. McGraw-Hill Higher Education, Burr Ridge, USA, p.17-18, 599.
[16]Razavi B, 2008. Fundamentals of Microelectronics. John Wiley & Sons Inc, Hoboken, USA, p.282-284.
[17]Redouté JM, Steyaert MSJ, 2010. EMI-resistant CMOS differential input stages. IEEE Trans Circ Syst I Regular Pap, 57(2):323-331.
[18]Redouté JM, Richelli A, 2015. A methodological approach to EMI resistant analog integrated circuit design. IEEE Electromagn Compat Mag, 4(2):92-100.
[19]Richelli A, 2012. Increasing EMI immunity in novel low-voltage CMOS OpAmps. IEEE Trans Electromagn Compat, 54(4):947-950.
[20]Richelli A, Colalongo L, Kovacs-Vajna ZM, 2003. Increasing the immunity to electromagnetic interferences of CMOS OpAmps. IEEE Trans Reliab, 52(3):349-353.
[21]Singh A, 2017. EMI harderend current mirror. IEEE Int Conf on Circuits and Systems, p.431-436.
[22]Wang GJ, Zhang YZ, Zhao Y, et al., 2022. Design of GPR transmitting pulse signal based on FPGA. 41st Chinese Control Conf, p.3070-3074.
[23]Wang HY, Li JY, Li H, et al., 2008. Experimental study and SPICE simulation of CMOS inverters latch-up effects due to high power microwave interference. Prog Electromagn Res, 87:313-330.
[24]Wang HY, Hu B, Zou H, et al., 2017. Circuit modeling and simulation of CMOS circuits latchup induced by microwave pulse injection. Progress in Electromagnetics Research Symp-Fall, p.2988-2992.
[25]Wunsch DC, Bell RR, 1968. Determination of threshold failure levels of semiconductor diodes and transistors due to pulse voltages. IEEE Trans Nucl Sci, 15(6):244-259.
[26]Yamashina M, Yamada H, 1992. An MOS current mode logic (MCML) circuit for low-power sub-GHz processors. IEICE Trans Electron, E75-C(10):1181-1187.
[27]Yao MQ, Sun X, 2019. He Figure transformation algorithm based on current-type CMOS circuit. 14th IEEE Int Conf on Electronic Measurement & Instruments, p.279-285.
[28]Zupan D, Deutschmann B, 2020. Comparison of EMI improved differential input pair structures within an integrated folded cascode operational transconductance amplifier. Austrochip Workshop on Microelectronics, p.47-52.
Open peer comments: Debate/Discuss/Question/Opinion
<1>