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CLC number: TN92; TN43
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2021-02-24
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Citations: Bibtex RefMan EndNote GB/T7714
A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based gm-boosting techniques
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Hongchen Chen, Haoshen Zhu, Liang Wu, Wenquan Che, Quan Xue. A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based gm-boosting techniques[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(4): 586-598.
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author="Hongchen Chen, Haoshen Zhu, Liang Wu, Wenquan Che, Quan Xue",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="22",
number="4",
pages="586-598",
year="2021",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2000510"
}
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%A Wenquan Che
%A Quan Xue
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%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2000510
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T1 - A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based gm-boosting techniques
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A1 - Haoshen Zhu
A1 - Liang Wu
A1 - Wenquan Che
A1 - Quan Xue
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 22
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SP - 586
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%@ 2095-9184
Y1 - 2021
PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.2000510
Abstract: A 9.8–30.1 GHz CMOS low-noise amplifier (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on common-gate (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and transformer-based gm-boosting techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm CMOS technology, the LNA chip occupies an area of only 0.2 mm2 and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.
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