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On-line Access: 2017-03-10
Received: 2015-10-28
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A novel ternary half adder and multiplier based on carbon nanotube field effect transistors
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Sepehr Tabrizchi, Nooshin Azimi, Keivan Navi. A novel ternary half adder and multiplier based on carbon nanotube field effect transistors[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(3): 423-433.
@article{title="A novel ternary half adder and multiplier based on carbon nanotube field effect transistors",
author="Sepehr Tabrizchi, Nooshin Azimi, Keivan Navi",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="18",
number="3",
pages="423-433",
year="2017",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.1500366"
}
%0 Journal Article
%T A novel ternary half adder and multiplier based on carbon nanotube field effect transistors
%A Sepehr Tabrizchi
%A Nooshin Azimi
%A Keivan Navi
%J Frontiers of Information Technology & Electronic Engineering
%V 18
%N 3
%P 423-433
%@ 2095-9184
%D 2017
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.1500366
TY - JOUR
T1 - A novel ternary half adder and multiplier based on carbon nanotube field effect transistors
A1 - Sepehr Tabrizchi
A1 - Nooshin Azimi
A1 - Keivan Navi
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 18
IS - 3
SP - 423
EP - 433
%@ 2095-9184
Y1 - 2017
PB - Zhejiang University Press & Springer
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DOI - 10.1631/FITEE.1500366
Abstract: A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.
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