| index | Title |
| 1 | A parallel and scalable digital architecture for training support vector machines Author(s):Kui-kang Cao, Hai-bin Shen, Hua-fe... Clicked:10699 Download:4032 Cited:6 <Full Text> Journal of Zhejiang University Science C 2010 Vol.11 No.8 P.620-628 DOI:10.1631/jzus.C0910500 |
| 2 | An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable g... Author(s):Zhen-guo Ma, Feng Yu, Rui-feng Ge,... Clicked:12475 Download:4198 Cited:1 <Full Text> Journal of Zhejiang University Science C 2011 Vol.12 No.4 P.323-329 DOI:10.1631/jzus.C1000258 |
| 3 | High-speed, fixed-latency serial links with Xilinx FPGAs Author(s):Xue Liu, Qing-xu Deng, Bo-ning Hou... Clicked:10301 Download:5425 Cited:1 <Full Text> Journal of Zhejiang University Science C 2014 Vol.15 No.2 P.153-160 DOI:10.1631/jzus.C1300249 |
| 4 | Synchronization stability between initial-dependent oscillators with periodical and chaotic oscillation Author(s):Fu-qiang Wu, Jun Ma, Guo-dong Ren Clicked:6790 Download:4562 Cited:0 <Full Text> <PPT> 2549 Journal of Zhejiang University Science A 2018 Vol.19 No.12 P.889-903 DOI:10.1631/jzus.A1800334 |
| 5 | Implementation of PRINCE with resource-efficient structures based on FPGAs Author(s):Lang Li, Jingya Feng, Botao Liu, Y... Clicked:12385 Download:10166 Cited:0 <Full Text> <PPT> 2367 Frontiers of Information Technology & Electronic Engineering 2021 Vol.22 No.11 P.1505-1516 DOI:10.1631/FITEE.2000688 |
| 6 | A BCH error correction scheme applied to FPGA with embedded memory Author(s):Yang Liu, Jie Li, Han Wang, Debiao... Clicked:8393 Download:11119 Cited:0 <Full Text> <PPT> 2505 Frontiers of Information Technology & Electronic Engineering 2021 Vol.22 No.8 P.1127-1139 DOI:10.1631/FITEE.2000323 |
| 7 | Dynamic power-gating for leakage power reduction in FPGAs Author(s):Hadi JAHANIRAD Clicked:6040 Download:8479 Cited:0 <Full Text> <PPT> 767 Frontiers of Information Technology & Electronic Engineering 2023 Vol.24 No.4 P.582-598 DOI:10.1631/FITEE.2200084 |
| 8 | Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH Author(s):Zhengzhou CAO, Guozhu LIU, Yanfei ... Clicked:3403 Download:2781 Cited:0 <Full Text> <PPT> 917 Frontiers of Information Technology & Electronic Engineering 2024 Vol.25 No.4 P.485-499 DOI:10.1631/FITEE.2300454 |
| 9 | Vina-FPGA2: a high-level parallelized hardware-accelerated molecular docking tool based on the inter-module... Author(s):Ming LING, Shidi TANG, Ruiqi CHEN,... Clicked:853 Download:509 Cited:0 <Full Text> Frontiers of Information Technology & Electronic Engineering 2025 Vol.26 No.11 P.2215-2230 DOI:10.1631/FITEE.2400941 |