| index | Title |
| 1 | DVB-S2 inner receiver design for broadcasting mode Author(s):YANG Jian-xiao, WANG Kuang, ZOU Zh... Clicked:7094 Download:7749 Cited:1 <Full Text> Journal of Zhejiang University Science A 2007 Vol.8 No.1 P.28-35 DOI:10.1631/jzus.2007.A0028 |
| 2 | A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic Author(s):ZENG Yong-hong, ZOU Xue-cheng, LIU... Clicked:8612 Download:4749 Cited:2 <Full Text> Journal of Zhejiang University Science A 2007 Vol.8 No.10 P.1553-1559 DOI:10.1631/jzus.2007.A1553 |
| 3 | High-performance hardware architecture of elliptic curve cryptography processor over GF(2163 Author(s):Yong-ping DAN, Xue-cheng ZOU, Zhen... Clicked:7595 Download:4628 Cited:5 <Full Text> Journal of Zhejiang University Science A 2009 Vol.10 No.2 P.301-310 DOI:10.1631/jzus.A0820024 |
| 4 | Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder Author(s):Wan-yi LI, Lu YU Clicked:7932 Download:4958 Cited:0 <Full Text> Journal of Zhejiang University Science A 2008 Vol.9 No.12 P.1638-1643 DOI:10.1631/jzus.A0820112 |
| 5 | A power-aware code-compression design for RISC/VLIW architecture Author(s):Che-Wei Lin, Chang Hong Lin, Wei J... Clicked:9438 Download:3912 Cited:1 <Full Text> Journal of Zhejiang University Science C 2011 Vol.12 No.8 P.629-637 DOI:10.1631/jzus.C1000321 |
| 6 | Efficient implementation of a cubic-convolution based image scaling engine Author(s):Xiang Wang, Yong Ding, Ming-yu Liu... Clicked:10313 Download:5642 Cited:4 <Full Text> Journal of Zhejiang University Science C 2011 Vol.12 No.9 P.743-753 DOI:10.1631/jzus.C1100040 |
| 7 | A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system Author(s):Ji-nan Leng, Lei Xie, Hui-fang Che... Clicked:9590 Download:4995 Cited:4 <Full Text> Journal of Zhejiang University Science C 2011 Vol.12 No.12 P.1021-1030 DOI:10.1631/jzus.C1100071 |
| 8 | Embedded software and hardware implementation system for a human machine interface based on ISOAgLib Author(s):Enkhbaatar Tumenjargal, Luubaatar ... Clicked:9880 Download:7988 Cited:0 <Full Text> Journal of Zhejiang University Science C 2013 Vol.14 No.3 P.155-166 DOI:10.1631/jzus.C1200270 |
| 9 | Recent advances in efficient computation of deep convolutional neural networks Author(s):Jian Cheng, Pei-song Wang, Gang Li... Clicked:12525 Download:5418 Cited:0 <Full Text> <PPT> 2881 Frontiers of Information Technology & Electronic Engineering 2018 Vol.19 No.1 P.64-77 DOI:10.1631/FITEE.1700789 |
| 10 | Correlation power attack on a message authentication code based on SM3 Author(s):Ye Yuan, Kai-ge Qu, Li-ji Wu, Jia-... Clicked:9763 Download:4295 Cited:0 <Full Text> <PPT> 2368 Frontiers of Information Technology & Electronic Engineering 2019 Vol.20 No.7 P.930-945 DOI:10.1631/FITEE.1800312 |
| 11 | Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA Author(s):Vijay Dahiphale, Gaurav Bansod, An... Clicked:8529 Download:4897 Cited:0 <Full Text> <PPT> 2361 Frontiers of Information Technology & Electronic Engineering 2020 Vol.21 No.4 P.615-628 DOI:10.1631/FITEE.1800681 |
| 12 | Implementation of PRINCE with resource-efficient structures based on FPGAs Author(s):Lang Li, Jingya Feng, Botao Liu, Y... Clicked:12614 Download:10343 Cited:0 <Full Text> <PPT> 2407 Frontiers of Information Technology & Electronic Engineering 2021 Vol.22 No.11 P.1505-1516 DOI:10.1631/FITEE.2000688 |
| 13 | COPPER: a combinatorial optimization problem solver with processing-in-memory architecture Author(s):Qiankun WANG, Xingchen LI, Bingzhe... Clicked:4438 Download:8910 Cited:0 <Full Text> <PPT> 1460 Frontiers of Information Technology & Electronic Engineering 2023 Vol.24 No.5 P.731-741 DOI:10.1631/FITEE.2200463 |
| 14 | Digital-to-analog converter free architecture for digital reconfigurable intelligent surface Author(s):Miaoran PENG, Jinhao KAN, Lixia XI... Clicked:4549 Download:6149 Cited:0 <Full Text> <PPT> 1220 Frontiers of Information Technology & Electronic Engineering 2023 Vol.24 No.12 P.1752-1762 DOI:10.1631/FITEE.2300133 |
| 15 | Vina-FPGA2: a high-level parallelized hardware-accelerated molecular docking tool based on the inter-module... Author(s):Ming LING, Shidi TANG, Ruiqi CHEN,... Clicked:956 Download:546 Cited:0 <Full Text> Frontiers of Information Technology & Electronic Engineering 2025 Vol.26 No.11 P.2215-2230 DOI:10.1631/FITEE.2400941 |