| index | Title |
| 16 | Correlation power attack on a message authentication code based on SM3 Author(s):Ye Yuan, Kai-ge Qu, Li-ji Wu, Jia-wei Ma, Xiang-min Zhang Clicked:9374 Download:3619 Cited:0 <Full Text> <PPT> 2219 Frontiers of Information Technology & Electronic Engineering 2019 Vol.20 No.7 P.930-945 DOI:10.1631/FITEE.1800312 |
| 17 | Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA Author(s):Vijay Dahiphale, Gaurav Bansod, Ankur Zambare, Narayan Pisharoty Clicked:8171 Download:4152 Cited:0 <Full Text> <PPT> 2241 Frontiers of Information Technology & Electronic Engineering 2020 Vol.21 No.4 P.615-628 DOI:10.1631/FITEE.1800681 |
| 18 | Dynamic analysis, FPGA implementation, and cryptographic application of an autonomous 5D chaotic system with offset boosting Author(s):Sifeu Takougang Kingni, Karthikeyan Rajagopal, Serdar Çiçek, Ashokkumar Srinivasan, Anitha Karthikeyan Clicked:9817 Download:9241 Cited:0 <Full Text> Frontiers of Information Technology & Electronic Engineering 2020 Vol.21 No.6 P.950-961 DOI:10.1631/FITEE.1900167 |
| 19 | Implementation of PRINCE with resource-efficient structures based on FPGAs Author(s):Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li Clicked:11895 Download:9453 Cited:0 <Full Text> <PPT> 2268 Frontiers of Information Technology & Electronic Engineering 2021 Vol.22 No.11 P.1505-1516 DOI:10.1631/FITEE.2000688 |
| 20 | A BCH error correction scheme applied to FPGA with embedded memory Author(s):Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li Clicked:8105 Download:10147 Cited:0 <Full Text> <PPT> 2409 Frontiers of Information Technology & Electronic Engineering 2021 Vol.22 No.8 P.1127-1139 DOI:10.1631/FITEE.2000323 |
| 21 | Dynamic power-gating for leakage power reduction in FPGAs Author(s):Hadi JAHANIRAD Clicked:5746 Download:7434 Cited:0 <Full Text> <PPT> 716 Frontiers of Information Technology & Electronic Engineering 2023 Vol.24 No.4 P.582-598 DOI:10.1631/FITEE.2200084 |
| 22 | Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH Author(s):Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU Clicked:3082 Download:2245 Cited:0 <Full Text> <PPT> 816 Frontiers of Information Technology & Electronic Engineering 2024 Vol.25 No.4 P.485-499 DOI:10.1631/FITEE.2300454 |
| 23 | Vina-FPGA2: a high-level parallelized hardware-accelerated molecular docking tool based on the inter-module pipeline Author(s):Ming LING, Shidi TANG, Ruiqi CHEN, Xin LI, Yanxiang ZHU Clicked:620 Download:417 Cited:0 <Full Text> Frontiers of Information Technology & Electronic Engineering 2025 Vol.26 No.11 P.2215-2230 DOI:10.1631/FITEE.2400941 |
