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8 results found in all.

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1	A parallel and scalable digital architecture for training support vector machines Author(s):Kui-kang Cao, Hai-bin Shen, Hua-feng Chen Clicked:9334 Download:3490 Cited:6 <Full Text> Journal of Zhejiang University Science C 2010 Vol.11 No.8 P.620-628 DOI:10.1631/jzus.C0910500
2	An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays Author(s):Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang Clicked:10708 Download:3458 Cited:1 <Full Text> Journal of Zhejiang University Science C 2011 Vol.12 No.4 P.323-329 DOI:10.1631/jzus.C1000258
3	High-speed, fixed-latency serial links with Xilinx FPGAs Author(s):Xue Liu, Qing-xu Deng, Bo-ning Hou, Ze-ke Wang Clicked:8739 Download:3791 Cited:1 <Full Text> Journal of Zhejiang University Science C 2014 Vol.15 No.2 P.153-160 DOI:10.1631/jzus.C1300249
4	Synchronization stability between initial-dependent oscillators with periodical and chaotic oscillation Author(s):Fu-qiang Wu, Jun Ma, Guo-dong Ren Clicked:4298 Download:2713 Cited:0 <Full Text> <PPT> 1941 Journal of Zhejiang University Science A 2018 Vol.19 No.12 P.889-903 DOI:10.1631/jzus.A1800334
5	Implementation of PRINCE with resource-efficient structures based on FPGAs Author(s):Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li Clicked:7782 Download:7143 Cited:0 <Full Text> <PPT> 1634 Frontiers of Information Technology & Electronic Engineering 2021 Vol.22 No.11 P.1505-1516 DOI:10.1631/FITEE.2000688
6	A BCH error correction scheme applied to FPGA with embedded memory Author(s):Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li Clicked:6566 Download:7056 Cited:0 <Full Text> <PPT> 1772 Frontiers of Information Technology & Electronic Engineering 2021 Vol.22 No.8 P.1127-1139 DOI:10.1631/FITEE.2000323
7	Dynamic power-gating for leakage power reduction in FPGAs Author(s):Hadi JAHANIRAD Clicked:4497 Download:5483 Cited:0 <Full Text> <PPT> 405 Frontiers of Information Technology & Electronic Engineering 2023 Vol.24 No.4 P.582-598 DOI:10.1631/FITEE.2200084
8	Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH Author(s):Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU Clicked:1716 Download:1159 Cited:0 <Full Text> <PPT> 415 Frontiers of Information Technology & Electronic Engineering 2024 Vol.25 No.4 P.485-499 DOI:10.1631/FITEE.2300454

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