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CLC number: TN919.8
On-line Access: 2024-08-27
Received: 2023-10-17
Revision Accepted: 2024-05-08
Crosschecked: 2011-05-05
Cited: 3
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An efficient hardware design for HDTV H.264/AVC encoder
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Liang Wei, Dan-dan Ding, Juan Du, Bin-bin Yu, Lu Yu. An efficient hardware design for HDTV H.264/AVC encoder[J]. Journal of Zhejiang University Science C, 2011, 12(6): 499-506.
@article{title="An efficient hardware design for HDTV H.264/AVC encoder",
author="Liang Wei, Dan-dan Ding, Juan Du, Bin-bin Yu, Lu Yu",
journal="Journal of Zhejiang University Science C",
volume="12",
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pages="499-506",
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publisher="Zhejiang University Press & Springer",
doi="10.1631/jzus.C1000201"
}
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Abstract: This paper presents a hardware efficient high definition television (HDTV) encoder for h.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of h.264/AVC high profile.
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