Full Text:   <2688>

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CLC number: TN432

On-line Access: 2016-03-07

Received: 2015-07-06

Revision Accepted: 2015-11-18

Crosschecked: 2016-02-20

Cited: 1

Clicked: 6350

Citations:  Bibtex RefMan EndNote GB/T7714


Li-rong Zheng


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Frontiers of Information Technology & Electronic Engineering  2016 Vol.17 No.3 P.258-264


Design and simulation of a standing wave oscillator based PLL

Author(s):  Wei Zhang, You-de Hu, Li-rong Zheng

Affiliation(s):  State Key Lab of ASIC & System, Fudan University, Shanghai 200433, China; more

Corresponding email(s):   wei_zhang@fudan.edu.cn, lirong@kth.se

Key Words:  Standing wave oscillator (SWO), Clock distribution, Phase locked loop (PLL), Varactor

Wei Zhang, You-de Hu, Li-rong Zheng. Design and simulation of a standing wave oscillator based PLL[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(3): 258-264.

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A1 - Wei Zhang
A1 - You-de Hu
A1 - Li-rong Zheng
J0 - Frontiers of Information Technology & Electronic Engineering
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DOI - 10.1631/FITEE.1500210

A standing wave oscillator (SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor (IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop (PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P complementary metal-oxide-semiconductor (CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

This paper shows an interesting and meaningful design of a standing wave oscillator based PLL, which has a potential for future PLL application to reduced clock power and clock skew.




Darkslateblue:Affiliate; Royal Blue:Author; Turquoise:Article


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