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Abstract: We present a 31–45.5 GHz injection-locked frequency divider (ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 dBm. The power consumption is 2.88 mW under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.

基于90 nm CMOS工艺的31–45.5 GHz注入式锁定分频器

随着无线通信技术迅速发展，毫米波频段因其丰富频谱资源受到越来越多关注。为充分利用该波段丰富频谱资源，毫米波集成电路设计的首要挑战在于高的工作频率和宽的频率覆盖范围。就毫米波锁相环集成电路设计而言，设计一款同时具备高工作频率和宽锁定范围的分频器具有重要意义。注入式锁定分频器因其高工作频率和低功耗等特点成为毫米波分频器设计的首选，但其工作频率范围通常非常窄。本文针对传统的注入式锁定分频器，分析其锁定频率范围的影响因素，并改进电路结构提高其锁定频率范围。 为解决传统注入式分频器锁定范围窄的难题，在电路中引入一个NMOS晶体管，通过调节其栅极直流电压控制其电阻值，获得一个可调节电阻器。结合注入式分频器锁定范围公式，可以发现栅极直流电平越高，对应可调电阻器的电阻值越小，分频器的锁定范围越宽，代价是分频器的输出信号功率降低。实际应用中，可以合理设置NMOS晶体管的栅极电压，在确保足够输出信号功率的前提下获得尽可能宽的锁定范围。 从理论上分析影响锁定范围的关键因素，针对相关参量，提出优化设计的方向，并改进电路结构，获得具备高工作频率宽锁定范围的低功耗注入式锁定分频器。 针对本文提出的电路结构，在实际应用中，根据不同需求设置合理的NMOS晶体管栅极电压，即可获得所要求的宽频率带宽或高输出功率。仿真和测试结果验证了这一结论。
CMOS；注入式锁定分频器；毫米波；宽锁定范围；单片微波集成电路

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